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PDSP16540
FEBRUARY 1995
ADVANCE INFORMATION
DS3715 - 2.1
PDSP16540
32K BUCKET BUFFER
(Supersedes version in December 1993 Digital Video & Digital Signal Processing IC Handbook, HB3923-1)
The PDSP16540 Bucket Buffer is for use in systems which
require a reservoir in which a block of data is accumulated,
whilst previous data is being transferred to other system
elements and then processed. It thus prevents the loss of
incoming data whilst the previous block is being processed.
Like a FIFO all address are generated internally.
It differs from a normal FIFO, however, by allowing the
user to define both the length of the data block and also the
amount of the old data to be re-read before the new data is
added. The latter feature supports the block overlapping
requirements of Digital Signal Processing Systems perform-
ing Fast Fourier Transforms. It also provides wide, 32 bit, input
and output buses, unlike normal byte wide FIFO's. This wide
configuration supports the16 bit real and imaginary compo-
nents of the complex data found in many DSP systems.
In particular, the device can be directly connected to the
PDSP16510 FFT Processor without any external logic. The
FFT Processor requires the support of an input buffer when
1024 point transforms are to be continuously performed and
no incoming data is to remain un-processed.
The number of words, which are read as a complete
block, can be programmed in multiples of 32 up to a maximum
of 1024. The amount of new data in this block can separately
be programmed in multiples of 32 words. In this manner the
percentage of new data in a complete block is under the
control of the user, and the device is not restricted to only
supporting the requirements of the PDSP16510.
A Read Me Flag is raised at a user defined point during
the loading of new data. This allows the next system compo-
nent to prepare itself to accept data. Data is not actually
transferred, however, until all the user defined amount of new
data has been loaded, and a Data Available Flag goes active.
The gap between the two flags can be programmed to provide
sufficient time to prepare the device which is to accept data
from the buffer. This provide a much more flexible solution
than the simple Full Flag offered by a standard FIFO.
FEATURES
s
1K x 32 bit dual port RAM for use as a reservoir in
data flow systems
s
s
s
Up to 40 MHz read rates and 16 MHz write rates
Buffer size user programmable up to 1k words
A user programmble amount of old data can be re-
read before new data is added
s
Provides the input buffer requirements for the
PDSP16510 FFT Processor when 1024 point
continuous transforms are performed
s
s
User programmable get ready to Read Me Flag
Data Available Flag indicates the required amount of
new data has been acquired
s
84 Pin PGA or 132 Pin QFP
WRITE STROBE
WRITE
ENABLE
READ STROBE
ASSOCIATED PRODUCTS
SYNC LOGIC
RESET
READ
1K X 32 BIT
DUAL PORT
RAM
WRITE
ADDRESS
READ
ADDRESS
32 BIT
O/P
DATA
READ
ME
FLAG
PDSP16510
FFT Processor
PDSP16520
Quad Port Synchronous RAM
PDSP16116
Complex Multiplier
PDSP16318
Complex Accumulator
PDSP16330
Cartesian to Polar Converter
PDSP16340
Polar to Cartesian Converter
MODE
CONTROL
32 BIT
I/P
DATA
WRITE
CONTROL LOGIC
DATA
AVAIL
FLAG
Figure 1. Simplified Block Diagram
1
PDSP16540
NAME
IP31:0
D31:0
TYPE
I/P
O/P
SIGNAL DESCRIPTION
32 bit input bus. If MD5 is high, pins IP16:31 are redundant
32 bit output bus. This bus will be high impedance until the Data Available Flag is active. It
then remains low impedance until the required amount of data has been read. D15:0
become inputs during reset, and may be used to define the operating conditions.
RS
WS
I/P
I/P
The read strobe must be continuous, and the rising edge transfers data to the output pins.
Write strobe used to load data into the internal RAM. This strobe may be asynchronous to
the read strobe, and may be continuous or intermittent.
WEN
DAV
I/P
O/P
Write enable which when low allows the write strobe to load data.
Data Available Flag. This signal goes active low when the required amount of new data has
been written to the RAM. The complete block of data will then be read from the RAM in
sequence using the read strobe. The next system component must be ready to accept the
information, which will consist of both new and old data, in amounts defined by MD2:1. The
flag will go in-active for one read strobe period every time new data is written to the RAM,
and stays in-active when the complete block has been transferred.
RMF
O/P
Read Me Flag. This signal goes active high when a user defined amount of new data has
been written to the RAM. It can go active before DAV goes active, and thus allows the
system to prepare itself for data when it becomes available. It stays active until the complete
block has been read.
MD0
I/P
When MD0 is low the block length is 1024 words. When it is high the block length is defined
in groups of 32 words by the data on D4:0 during reset.
MD2:1
MD2:1 define the amount of new data within the block length as defined above. The options
are 1024 (00), 512 (01), 256 (10), or the number defined in groups of 32 words by D9:5
during reset (11). When the number of new words is less than the block length defined by
MD0, the first words read from the RAM will be data previously stored.
MD4:3
I/P
MD4:3 define the number of new words which are written before the Read Me Flag goes
active. The options are 1024, 512, 256 or the number defined in groups of 16 words by
D15:10 during reset.
MD5
I/P
When this pin is high the device will support the real transform mode of the PDSP16510.
Only IP15:0 input pins are then used and 2 blocks are acquired before the flags go active.
Both blocks are then read in parallel using the 32 output pins.
RES
I/P
When this pin is low outputs D15:0 become inputs, which are used to define the operating
mode if the internal options have not been selected. The input can be power on reset.
GND
VCC
I/P
I/P
Four ground pins. All must be connected
Four +5 volt pins.All must be connected
2
PDSP16540
N
D7
D8
D10
D12
D14
VDD
D17
GND
D19
D21
D23
D25
D26
M
D6
D9
D11
D13
D15
D16
D18
D20
D22
D24
D27
L
D4
D5
D28
D29
K
D2
D3
D30
D31
J
D0
D1
MD0
MD1
H
GND
RMF
MD2
GND
G
RS
WEN
MD3
MD4
F
VDD
DAV
MD5
VDD
E
WS
IP
0
IP
31
RES
D
IP
1
IP
2
IP
29
IP
30
C
IP
3
IP
4
IP
27
IP
28
B
IP
5
IP
8
IP
10
IP
12
IP
14
IP
16
IP
17
IP
19
IP
21
IP
23
IP
26
A
IP
6
IP
7
IP
9
IP
11
IP
13
VDD
IP
15
GND
IP
18
IP
20
IP
22
IP
24
IP
25
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Out Diagram - Bottom View (84pin PGA - AC84)
FUNCTIONAL DESCRIPTION
The PDSP16540 is designed for use in synchronous data
flow systems in which the transfer between system elements
is contolled by a continuously available system clock. This
system clock is usually at the maximum rate that the system
elements will allow, since it is governing the rate at which
processing can be performed on the acquired data. The rate
at which external data is actually inputed to the system ( the
sampling rate in DSP terminology ) is usually much slower
than the internal system, or computational, rate. The
PDSP16540 then provides a reservoir for data which is
acquired at the sampling rate and then processed with the
higher speed system clock rate.
Data is written to the RAM using an asynchronous write
strobe when a write enable input is active. The enbling signal
must meet the set up and hold times given in Table 1. Data is
read from the RAM using a read strobe which is expected to
be continuously availble and not to just go active when read
operations are actually needed. It is normally the high speed
system clock discussed earlier. All RAM addresses are
generated internally since the device is partitioning consecu-
3
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