MC100LVEL40
3.3/5V ECL Differential
Phase−Frequency Detector
Description
The MC100LVEL40 is a three state phase frequency−detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V power supply.
When the reference (R) and the feedback (FB) inputs are unequal in
frequency and/or phase the differential up (U) and down (D) outputs
will provide pulse streams which when subtracted and integrated
provide an error voltage for control of a VCO.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
For application information, refer to AND8040/D, “Phase Lock
Loop Operation.”
The 100 Series Contains Temperature Compensation
Features
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MARKING
DIAGRAM
20
20
1
SO−20
DW SUFFIX
CASE 751D
100LVEL40
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
250 MHz Typical Bandwidth
•
PECL Mode Operating Range:
*For additional marking information, refer to
Application Note AND8002/D.
V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
•
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
−3.0
V to
−5.5
V
•
Internal Input Pulldown Resistor
•
Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 8
1
Publication Order Number:
MC100LVEL40/D
MC100LVEL40
NC V
CCO
20
19
U
18
U
17
V
EE
16
D
15
D
14
V
CCO
NC
13
12
NC
11
Table 1. PIN DESCRIPTION
PIN
U, U
D, D
FB, FB
R, R
V
BB
V
CC
, V
CCO
V
EE
NC
FUNCTION
ECL Up Differential Outputs
ECL Down Differential Outputs
ECL Feedback Differential Inputs
ECL Reference Differential Inputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
1
NC
2
NC
3
R
4
R
5
V
BB
6
FB
7
FB
8
V
CC
9
NC
10
NC
Warning: All V
CC
, V
CCO
, and V
EE
pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 20−Lead Pinout
(Top View)
R
R
V
BB
V
EE
S
R
Q
U
U
D
R
FB
FB
S
Q
D
Figure 2. Logic Diagram
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity (Note 1)
SOIC−20
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Pb Pkg
Level 1
Value
> 2 kV
Pb−Free Pkg
Level 3
UL 94 V−0 @ 0.125 in
356 Devices
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2
MC100LVEL40
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
SOIC−20
SOIC−20
SOIC−20
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
±
0.5
−40
to +85
−65
to +150
90
306
30 to 35
265
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V, V
EE
= 0 V (Note 2)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Note 7)
Vpp < 500 mV
Vpp
y
500 mV
Input HIGH Current
Input LOW Current
Others
R, FB
0.5
−300
2215
1470
2135
1490
1.92
Min
Typ
38
2295
1605
Max
45
2420
1745
2420
1825
2.04
2275
1490
2135
1490
1.92
Min
25°C
Typ
38
2345
1595
Max
47
2420
1380
2420
1825
2.04
2275
1490
2135
1490
1.92
Min
85°C
Typ
38
2345
1595
Max
47
2420
1680
2420
1825
2.04
Unit
mA
mV
mV
mV
mV
V
1.3
1.5
3.3
3.3
150
1.2
1.4
0.5
−300
3.3
3.3
150
1.2
1.4
0.5
−300
3.3
3.3
150
V
V
mA
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±
0.3 V.
3. Outputs are terminated through a 50
W
resistor to V
CC
−
2 V.
4. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and
1 V.
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3
MC100LVEL40
Table 5. LVNECL DC CHARACTERISTICS
V
CC
= 0 V; V
EE
=
−3.0
V (Note 5)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage
(Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common
Mode Range (Note 7)
Vpp < 500 mV
Vpp
y
500 mV
Input HIGH Current
Input LOW Current
Others
R, FB
0.5
−300
−1085
−1830
−1165
−1810
−1.38
Min
Typ
38
−1005
−1695
Max
45
−880
−1555
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
25°C
Typ
38
−955
−1705
Max
47
−880
−1620
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
85°C
Typ
38
−955
−1705
Max
47
−880
−1620
−880
−1475
−1.26
Unit
mA
mV
mV
mV
mV
V
−2.0
−1.8
−0.4
−0.4
150
−2.1
−1.9
0.5
−300
−0.4
−0.4
150
−2.1
−1.9
0.5
−300
−0.4
−0.4
150
V
V
mA
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±
0.3 V.
6. All loading with 50
W
resistor to V
CC
−
2 V.
7. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and
1 V.
Table 6. AC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0 V; V
EE
=
−3.3
V (Note 8)
−40°C
Symbol
Fmax
t
PLH
t
PHL
V
PP
t
JITTER
t
r
, t
f
Characteristic
Maximum Toggle Frequency
Propagation Delay
R to U, FB to D
430
1200
150
TBD
175
475
175
Min
Typ
TBD
630
1400
1000
450
1250
150
TBD
475
175
Max
Min
25°C
Typ
TBD
650
1450
1000
480
1370
150
TBD
475
Max
Min
85°C
Typ
TBD
680
1590
1000
Max
Unit
GHz
ps
mV
ps
ps
Input Swing (Differential Configuration)
(Note 9)
Cycle−to−Cycle Jitter
Output Rise/Fall Times
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. V
EE
can vary
±
0.3 V.
9. V
PP(
min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of
≈
40.
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4
MC100LVEL40
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
CC
−
2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
−
Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
MC10LVEL40DW
MC10LVEL40DWG
MC10LVEL40DWR2
MC10LVEL40DWR2G
Package
SOIC−20
SOIC−20
(Pb−Free)
SOIC−20
SOIC−20
(Pb−Free)
Shipping
†
38 Units / Rail
38 Units / Rail
1000 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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