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MC10135_02

Description
Dual J-K Master-Slave Flip-Flop
File Size112KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC10135_02 Overview

Dual J-K Master-Slave Flip-Flop

MC10135
Dual J-K Master-Slave
Flip-Flop
The MC10135 is a dual master–slave dc coupled J–K flip–flop.
Asynchro– nous set (S) and reset (R) are provided. The set and reset
inputs override the clock.
A common clock is provided with separate J–K inputs. When the
clock is static, the J–K inputs do not effect the output.
The output states of the flip–flop change on the positive transition of
the clock.
P
D
= 280 mW typ/pkg (No Load)
f
Tog
= 140 MHz typ
t
pd
= 3.0 ns typ
t
r
, t
f
= 2.5 ns typ (20%–80%)
DIP PIN ASSIGNMENT
V
CC1
Q1
Q1
R1
S1
K1
J1
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
Q2
Q2
R2
S2
K2
J2
C
S1 5
J1 7
K1 6
R1 4
C 9
S2 12
J2 10
K2
11
R2 13
Q2
Q2
15
14
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
MC10135L
AWLYYWW
LOGIC DIAGRAM
Q1
Q1
2
3
PDIP–16
P SUFFIX
CASE 648
1
MC10135P
AWLYYWW
1
PLCC–20
FN SUFFIX
CASE 775
10135
AWLYYWW
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 18 of the ON Semiconductor MECL
Data Book (DL122/D).
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
R–S TRUTH TABLE
R
L
L
H
H
S
L
H
L
H
Q
n+1
Q
n
H
L
N.D.
CLOCK J–K TRUTH TABLE*
J
L
H
L
H
K
L
L
H
H
Q
n+1
Q
n
L
H
Q
n
MC10135L
MC10135P
MC10135FN
N.D. = Not Defined
* Output states change on positive
transition of clock for J–K input
condition present.
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10135/D

MC10135_02 Related Products

MC10135_02 MC10135L MC10135 MC10135P MC10135FN
Description Dual J-K Master-Slave Flip-Flop Dual J-K Master-Slave Flip-Flop Dual J-K Master-Slave Flip-Flop Dual J-K Master-Slave Flip-Flop Dual J-K Master-Slave Flip-Flop
Is it Rohs certified? - incompatible - incompatible incompatible
Parts packaging code - DIP - DIP QLCC
package instruction - DIP-16 - DIP-16 LCC-20
Contacts - 16 - 16 20
Reach Compliance Code - _compli - _compli _compli
series - 10K - 10K 10K
JESD-30 code - R-CDIP-T16 - R-PDIP-T16 S-PQCC-J20
JESD-609 code - e0 - e0 e0
length - 19.495 mm - 19.175 mm 8.965 mm
Logic integrated circuit type - JBAR-KBAR FLIP-FLOP - JBAR-KBAR FLIP-FLOP JBAR-KBAR FLIP-FLOP
Maximum Frequency@Nom-Su - 5200000 Hz - 5200000 Hz 5200000 Hz
Number of digits - 2 - 2 2
Number of functions - 1 - 1 1
Number of terminals - 16 - 16 20
Maximum operating temperature - 85 °C - 85 °C 85 °C
Minimum operating temperature - -30 °C - -30 °C -30 °C
Output characteristics - OPEN-EMITTER - OPEN-EMITTER OPEN-EMITTER
Output polarity - COMPLEMENTARY - COMPLEMENTARY COMPLEMENTARY
Package body material - CERAMIC, METAL-SEALED COFIRED - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - DIP - DIP QCCJ
Encapsulate equivalent code - DIP16,.3 - DIP16,.3 LDCC20,.4SQ
Package shape - RECTANGULAR - RECTANGULAR SQUARE
Package form - IN-LINE - IN-LINE CHIP CARRIER
Peak Reflow Temperature (Celsius) - NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
power supply - -5.2 V - -5.2 V -5.2 V
Maximum supply current (ICC) - 75 mA - 75 mA 75 mA
propagation delay (tpd) - 4.5 ns - 4.5 ns 4.5 ns
Certification status - Not Qualified - Not Qualified Not Qualified
Maximum seat height - 5.08 mm - 4.44 mm 4.57 mm
surface mount - NO - NO YES
technology - ECL - ECL ECL
Temperature level - OTHER - OTHER OTHER
Terminal surface - Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form - THROUGH-HOLE - THROUGH-HOLE J BEND
Terminal pitch - 2.54 mm - 2.54 mm 1.27 mm
Terminal location - DUAL - DUAL QUAD
Maximum time at peak reflow temperature - NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
Trigger type - POSITIVE EDGE - POSITIVE EDGE POSITIVE EDGE
width - 7.62 mm - 7.62 mm 8.965 mm
minfmax - 125 MHz - 125 MHz 125 MHz
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