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MC10173FN

Description
Quad 2-Input Multiplexer/ Latch
Categorylogic    logic   
File Size111KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Download Datasheet Parametric Compare View All

MC10173FN Overview

Quad 2-Input Multiplexer/ Latch

MC10173FN Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQLCC
package instructionLCC-20
Contacts20
Reach Compliance Code_compli
Is SamacsysN
Other featuresFOUR 2:1 MUX FOLLOWED BY LATCH
series10K
JESD-30 codeS-PQCC-J20
JESD-609 codee0
length8.965 mm
Logic integrated circuit typeD LATCH
Number of digits4
Number of functions1
Number of entries2
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
Output characteristicsOPEN-EMITTER
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply-5.2 V
Maximum supply current (ICC)73 mA
Prop。Delay @ Nom-Su6.8 ns
propagation delay (tpd)6.8 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeLOW LEVEL
width8.965 mm
Base Number Matches1
MC10173
Quad 2-Input Multiplexer/
Latch
The MC10173 is a quad two channel multiplexer with latch. It
incorporates common clock and common data select inputs. The select
input determines which data input is enabled. A high (H) level enables
data inputs D00, D10, D20, and D30 and a low (L) level enables data
inputs D01, D11, D21, D31. Any change on the data input will be
reflected at the outputs while the clock is low. The outputs are latched
on the positive transition of the clock. While the clock is in the high
state, a change in the information present at the data inputs will not
affect the output information.
P
D
= 275 mW typ/pkg (No Load)
t
pd
= 2.5 ns typ
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
SELECT 9
1 Q0
PLCC–20
FN SUFFIX
CASE 775
A
WL
YY
WW
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
1
1
10173
AWLYYWW
MC10173P
AWLYYWW
MC10173L
AWLYYWW
D00 6
D01 5
D10 4
D11 3
2 Q1
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
D20 13
D21 12
15 Q2
Q0
Q1
D11
D10
D30 11
D31 10
CLOCK 7
14 Q3
D01
V
CC
= PIN 16
V
EE
= PIN 8
D00
CLOCK
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q2
Q3
D20
D21
D30
D31
SELECT
TRUTH TABLE
SELECT
H
L
X
CLOCK
L
L
H
Q0
n+1
D00
D01
Q0
n
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
MC10173L
MC10173P
MC10173FN
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10173/D

MC10173FN Related Products

MC10173FN MC10173L MC10173P MC10173_02 MC10173
Description Quad 2-Input Multiplexer/ Latch Quad 2-Input Multiplexer/ Latch Quad 2-Input Multiplexer/ Latch Quad 2-Input Multiplexer/ Latch Quad 2-Input Multiplexer/ Latch
Is it Rohs certified? incompatible incompatible incompatible - -
Parts packaging code QLCC DIP DIP - -
package instruction LCC-20 DIP-16 DIP-16 - -
Contacts 20 16 16 - -
Reach Compliance Code _compli _compli _compli - -
Other features FOUR 2:1 MUX FOLLOWED BY LATCH FOUR 2:1 MUX FOLLOWED BY LATCH FOUR 2:1 MUX FOLLOWED BY LATCH - -
series 10K 10K 10K - -
JESD-30 code S-PQCC-J20 R-CDIP-T16 R-PDIP-T16 - -
JESD-609 code e0 e0 e0 - -
length 8.965 mm 19.495 mm 19.175 mm - -
Logic integrated circuit type D LATCH D LATCH D LATCH - -
Number of digits 4 4 4 - -
Number of functions 1 1 1 - -
Number of entries 2 2 2 - -
Number of terminals 20 16 16 - -
Maximum operating temperature 85 °C 85 °C 85 °C - -
Minimum operating temperature -30 °C -30 °C -30 °C - -
Output characteristics OPEN-EMITTER OPEN-EMITTER OPEN-EMITTER - -
Output polarity TRUE TRUE TRUE - -
Package body material PLASTIC/EPOXY CERAMIC, METAL-SEALED COFIRED PLASTIC/EPOXY - -
encapsulated code QCCJ DIP DIP - -
Encapsulate equivalent code LDCC20,.4SQ DIP16,.3 DIP16,.3 - -
Package shape SQUARE RECTANGULAR RECTANGULAR - -
Package form CHIP CARRIER IN-LINE IN-LINE - -
power supply -5.2 V -5.2 V -5.2 V - -
Maximum supply current (ICC) 73 mA 73 mA 73 mA - -
Prop。Delay @ Nom-Su 6.8 ns 6.8 ns 6.8 ns - -
propagation delay (tpd) 6.8 ns 6.8 ns 6.8 ns - -
Certification status Not Qualified Not Qualified Not Qualified - -
Maximum seat height 4.57 mm 5.08 mm 4.44 mm - -
surface mount YES NO NO - -
technology ECL ECL ECL - -
Temperature level OTHER OTHER OTHER - -
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - -
Terminal form J BEND THROUGH-HOLE THROUGH-HOLE - -
Terminal pitch 1.27 mm 2.54 mm 2.54 mm - -
Terminal location QUAD DUAL DUAL - -
Trigger type LOW LEVEL LOW LEVEL LOW LEVEL - -
width 8.965 mm 7.62 mm 7.62 mm - -
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