MC10173
Quad 2-Input Multiplexer/
Latch
The MC10173 is a quad two channel multiplexer with latch. It
incorporates common clock and common data select inputs. The select
input determines which data input is enabled. A high (H) level enables
data inputs D00, D10, D20, and D30 and a low (L) level enables data
inputs D01, D11, D21, D31. Any change on the data input will be
reflected at the outputs while the clock is low. The outputs are latched
on the positive transition of the clock. While the clock is in the high
state, a change in the information present at the data inputs will not
affect the output information.
•
P
D
= 275 mW typ/pkg (No Load)
•
t
pd
= 2.5 ns typ
•
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
SELECT 9
1 Q0
PLCC–20
FN SUFFIX
CASE 775
A
WL
YY
WW
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
1
1
10173
AWLYYWW
MC10173P
AWLYYWW
MC10173L
AWLYYWW
D00 6
D01 5
D10 4
D11 3
2 Q1
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
D20 13
D21 12
15 Q2
Q0
Q1
D11
D10
D30 11
D31 10
CLOCK 7
14 Q3
D01
V
CC
= PIN 16
V
EE
= PIN 8
D00
CLOCK
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q2
Q3
D20
D21
D30
D31
SELECT
TRUTH TABLE
SELECT
H
L
X
CLOCK
L
L
H
Q0
n+1
D00
D01
Q0
n
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
MC10173L
MC10173P
MC10173FN
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10173/D
MC10173
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
Test
8
5
6
7
9
All
1
2
1
2
1
2
1
2
0.5
–1.060
–1.060
–1.890
–1.890
–1.080
–1.080
–1.655
–1.655
–0.890
–0.890
–1.675
–1.675
–30°C
Min
Max
73
470
470
400
400
0.5
–0.960
–0.960
–1.850
–1.850
–0.980
–0.980
–1.630
–1.630
–0.810
–0.810
–1.650
–1.650
Min
+25°C
Typ
Max
66
295
295
250
250
0.3
–0.890
–0.890
–1.825
–1.825
–0.910
–0.910
–1.595
–1.595
–0.700
–0.700
–1.615
–1.615
Min
+85°C
Max
73
295
295
250
250
Unit
mAdc
µAdc
Characteristic
Power Supply Drain Current
Input Current
Symbol
I
E
I
inH
I
inL
Output Voltage
Output Voltage
Threshold Voltage
Threshold Voltage
Logic 1
Logic 0
Logic 1
Logic 0
V
OH
V
OL
V
OHA
V
OLA
µAdc
Vdc
Vdc
Vdc
Vdc
ns
Switching Times (50Ω Load)
Propagation
Delay
Data Input
t
6+1+
t
6–1–
t
5+1+
t
5–1–
t
7–1+
t
7–1–
t
9+1+
t
9+1–
t
9–1+
t
9–1–
t
setup
t
setup
t
hold
t
hold
t+
t–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0.8
0.8
0.8
0.8
1.6
1.6
1.1
1.1
1.1
1.1
2.0
3.0
2.5
1.5
1.2
1.2
4.0
4.0
3.7
3.7
3.7
3.7
7.2
7.2
6.2
6.2
6.2
6.2
1.0
1.0
1.0
1.0
1.6
1.6
1.3
1.3
1.3
1.3
2.0
3.0
2.5
1.5
1.5
1.5
2.5
2.5
2.5
2.5
4.5
4.5
3.5
3.5
3.5
3.5
1.5
2.5
0.0
–0.5
2.0
2.0
3.5
3.5
3.5
3.5
3.5
3.5
6.8
6.8
5.7
5.7
5.7
5.7
1.1
1.1
1.1
1.1
1.4
1.4
1.2
1.2
1.2
1.2
2.0
3.0
2.5
1.5
1.4
1.4
4.0
4.0
5.3
5.3
5.3
5.3
6.8
6.8
6.7
6.7
6.7
6.7
Clock Input
Select Input
Setup TIme
Hold TIme
Rise Time
Fall Time
Data Input
Select Input
Data Input
Select Input
(20 to 80%)
(20 to 80%)
* V
ILmin
applied to each input pin, one at a time.
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MC10173
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
5
6
7
9
I
inL
Output Voltage
Output Voltage
Threshold Voltage
Threshold Voltage
Switching Times
Propagation Delay
Logic 1
Logic 0
Logic 1
Logic 0
(50Ω Load)
Data Input
t
6+1+
t
6–1–
t
5+1+
t
5–1–
t
7–1+
t
7–1–
t
9+1+
t
9+1–
t
9–1+
t
9–1–
t
setup
t
setup
t
hold
t
hold
t+
t–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
5
5
6
6
6
5
7
7
7
7
V
OH
V
OL
V
OHA
V
OLA
All
1
2
1
2
1
2
1
2
6, 9
5
9
9
9
+1.11V
9
9
5
6
7
9
*
7
7
7
7
7
7
7
7
+0.31V
7
7
7
7
Pulse In
6
6
5
5
5, 7
5, 7
9
9
9
9
5, 7
7, 9
5, 7
7, 9
7
7
6
5
6
5
Pulse Out
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V
IHmax
–0.890
–0.810
–0.700
V
ILmin
–1.890
–1.850
–1.825
V
IHAmin
–1.205
–1.105
–1.035
V
ILAmax
–1.500
–1.475
–1.440
V
EE
–5.2
–5.2
–5.2
(V
CC
)
Gnd
16
16
16
16
16
16
16
16
16
16
16
16
16
16
+2.0 V
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
–3.2 V
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Characteristic
Power Supply Drain Current
Input Current
Symbol
I
E
Clock Input
Select Input
Setup TIme
Hold TIme
Rise Time
Fall Time
Data Input
Select Input
Data Input
Select Input
(20 to 80%)
(20 to 80%)
* V
ILmin
applied to each input pin, one at a time.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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3
MC10173
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
B
–N–
Y BRK
D
–L–
–M–
W
D
X
V
A
Z
R
0.007 (0.180)
0.007 (0.180)
M
0.007 (0.180)
U
M
T L-M
M
S
N
S
S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D–D
T L-M
T L-M
S
N
N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1
K
C
E
0.004 (0.100)
G
G1
0.010 (0.250)
S
T L-M
J
–T–
SEATING
PLANE
F
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
---
0.025
---
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
---
0.020
2
_
10
_
0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
---
0.64
---
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
---
0.50
2
_
10
_
7.88
8.38
1.02
---
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4
MC10173
PACKAGE DIMENSIONS
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
–A–
16
9
–B–
1
8
C
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
---
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
_
15
_
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
---
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
_
15
_
0.51
1.01
–T–
SEATING
PLANE
N
E
F
D
G
16 PL
K
M
J
16 PL
0.25 (0.010)
M
M
T B
S
0.25 (0.010)
T A
S
–A–
16
9
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
B
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
_
10
_
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
_
10
_
0.51
1.01
F
S
C
L
–T–
H
G
D
16 PL
SEATING
PLANE
K
J
T A
M
M
0.25 (0.010)
M
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