Agilent ATF-531P8 High Linearity
Enhancement Mode
[1]
Pseudomorphic HEMT in
2x2 mm
2
LPCC
[3]
Package
Data Sheet
Features
• Single voltage operation
• High linearity and gain
• Low noise figure
Description
Agilent Technologies’s
ATF-531P8 is a single-voltage
high linearity, low noise
E-pHEMT housed in an 8-lead
JEDEC-standard leadless
plastic chip carrier (LPCC
[3]
)
package. The device is ideal as
a high linearity, low-noise,
medium-power amplifier. Its
operating frequency range is
from 50 MHz to 6 GHz.
The thermally efficient package
measures only 2 mm x 2 mm x
0.75 mm. Its backside
metalization provides excellent
thermal dissipation as well as
visual evidence of solder reflow.
The device has a Point MTTF of
over 300 years at a mounting
temperature of +85°C. All
devices are 100% RF & DC tested.
Note:
1. Enhancement mode technology employs a
single positive V
gs
, eliminating the need of
negative gate voltage associated with
conventional depletion mode devices.
2. Refer to reliability datasheet for detailed
MTTF data.
3. Conforms to JEDEC reference outline MO229
for DRP-N
4. Linearity Figure of Merit (LFOM) is essentially
OIP3 divided by DC bias power.
Pin Connections and
Package Marking
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
• Excellent uniformity in product
specifications
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Source
(Thermal/RF Gnd)
• Small package size:
2.0 x 2.0 x 0.75 mm
• Point MTTF > 300 years
[2]
• MSL-1 and lead-free
• Tape-and-reel packaging option
available
Bottom View
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Pin 8
3Px
Top View
Pin 7 (Drain)
Pin 6
Pin 5
Specifications
2 GHz; 4V, 135 mA (Typ.)
• 38 dBm output IP3
• 0.6 dB noise figure
• 20 dB gain
• 10.7 dB LFOM
[4]
• 24.5 dBm output power at 1 dB gain
compression
Applications
• Front-end LNA Q1 and Q2 driver or
pre-driver amplifier for Cellular/
PCS and WCDMA wireless
infrastructure
• Driver amplifier for WLAN,
WLL/RLL and MMDS applications
• General purpose discrete E-pHEMT
for other high linearity applications
Note:
Package marking provides orientation and
identification:
“3P” = Device Code
“x” = Date code indicates the month of
manufacture.
ATF-531P8 Absolute Maximum Ratings
[1]
Symbol
V
DS
V
GS
V
GD
I
DS
I
GS
P
diss
P
in max.
T
CH
T
STG
θ
ch_b
Parameter
Drain–Source Voltage
[2]
Gate–Source Voltage
[2]
Gate Drain Voltage
[2]
Drain Current
[2]
Gate Current
Total Power Dissipation
[3]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance
[4]
Units
V
V
V
mA
mA
W
dBm
°C
°C
°C/W
Absolute
Maximum
7
-5 to 1
-5 to 1
300
20
1
+24
150
-65 to 150
63
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureT
B
is 25°C.
Derate 16 mW/°C for T
B
> 87°C.
4. Thermal resistance measured using
150°C Liquid Crystal Measurement method.
5. Device can safely handle +24 dBm RF Input
Power provided IGS is limited to 20mA. IGS
at P1dB drive level is bias circuit dependent.
Product Consistency Distribution Charts at 2 GHz, 4V, 135 mA
[5,6]
400
0.9 V
300
0.8 V
180
150
120
90
60
-3 Std
+3 Std
Cpk = 1.0
Stdev = 0.14
160
Cpk = 1.2
Stdev = 0.71
120
I
DS
(mA)
200
0.7 V
80
-3 Std
+3 Std
100
0.6 V
40
30
0.5 V
0
0
1
2
3
4
5
6
7
V
DS
(V)
0
0
0
0.3
0.6
NF (dB)
0.9
1.2
35
36
37
38
OIP3 (dBm)
39
40
41
Figure 1. Typical I-V Curves
(Vgs = 0.1 per step).
Figure 2. NF
Nominal = 0.6, USL = 1.0.
Figure 3. OIP3
LSL = 35.5, Nominal = 38.1.
300
250
200
150
100
50
0
18.5
-3 Std
+3 Std
Cpk = 2.0
Stdev = 0.21
240
Stdev = 0.12
200
160
120
80
40
0
24.2
-3 Std
+3 Std
19.5
GAIN (dB)
20.5
21.5
24.4
24.6
24.8
25
25.2
P1dB (dBm)
Figure 4. Small Signal Gain
LSL = 18.5, Nominal = 20.2 dB, USL = 21.5.
Figure 5. P1dB
Nominal = 24.6.
Notes:
5. Distribution data sample size is 500 samples taken from 5 different wafers and 3 different lots.
Future wafers allocated to this product may have nominal values anywhere between the upper and
lower limits.
6. Measurements are made on production test board, which represents a trade-off between optimal
OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.
2
ATF-531P8 Electrical Specifications
T
A
= 25°C, DC bias for RF parameters is Vds = 4V and Ids = 135 mA unless otherwise specified.
Symbol
Vgs
Vth
Idss
Gm
Parameter and Test Condition
Operational Gate Voltage
Threshold Voltage
Saturated Drain Current
Transconductance
Vds = 4V, Ids = 135 mA
Vds = 4V, Ids = 8 mA
Vds = 4V, Vgs = 0V
Vds = 4.5V, Gm =
∆Idss/∆Vgs;
?Vgs = Vgs1 - Vgs2
Vgs1 = 0.6V, Vgs2 = 0.55V
Vds = 0V, Vgs = -4V
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
Offset BW = 5 MHz
Offset BW = 10 MHz
Units
V
V
µA
mmho
Min.
—
—
—
—
Typ.
0.68
0.3
3.7
650
Max.
—
—
—
—
Igss
NF
G
OIP3
P1dB
PAE
ACLR
Gate Leakage Current
Noise Figure
[1]
Gain
[1]
Output 3
rd
Order
Intercept Point
[1,2]
Output 1dB
Compressed
[1]
Power Added Efficiency
Adjacent Channel Leakage
Power Ratio
[1,3]
µA
dB
dB
dB
dB
dBm
dBm
dBm
dBm
%
%
dBc
dBc
-10
—
—
18.5
—
35.5
—
—
—
—
—
—
—
-0.34
0.6
0.6
20
25
38
37
24.5
23
57
45
-68
-64
—
1
—
21.5
—
—
—
—
—
—
—
—
—
Notes:
1. Measurements obtained using production test board described in Figure 6.
2. F1 = 2.00 GHz, F2 = 2.01 GHz and Pin = -10 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
– Test Model 1
– Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
– Freq = 2140 MHz
– Pin = -5 dBm
– Chan Integ Bw = 3.84 MHz
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag
= 0.66
Γ_ang
= -165°
(1.8 dB loss)
DUT
Output
Matching Circuit
Γ_mag
= 0.09
Γ_ang
= 118°
(1.1 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a
trade-off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.
3
2.2 pF
3.3 pF
50 Ohm
.02
λ
22 nH
15 Ohm
100 pF
2.2
µF
110 Ohm
.03
λ
110 Ohm
.03
λ
50 Ohm
.02
λ
4.7 pF
RF Input
DUT
12 nH
RF Output
Gate
DC Supply
Drain
DC Supply
Figure 7. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in
gate supply. Transmission line tapers, tee intersections, bias lines and parasitic values are not shown.
Gamma Load and Source at Optimum OIP3 Tuning Conditions
The device’s optimum OIP3 measurements were determined using a Maury load pull system at 4V, 135 mA
quiesent bias. The gamma load and source over frequency are shown in the table below:
Freq
(GHz)
0.9
2.0
3.9
5.8
Gamma Source
Mag
Ang
0.616
0.310
0.421
0.402
-37.1
34.5
167.5
-162.8
Gamma Load
Mag
Ang
0.249
0.285
0.437
0.418
130.0
168.3
-161.6
-134.1
OIP3
(dBm)
40.3
41.5
41.5
41.0
Gain
(dB)
16.5
13.4
10.5
7.9
P1dB
(dBm)
23.4
24.8
24.7
24.7
PAE
(%)
43.2
51.9
42.8
36.6
4
ATF-531P8 Typical Performance Curves
(at 25°C unless specified otherwise)
Tuned for Optimal OIP3
45
45
45
40
40
40
OIP3 (dBm)
OIP3 (dBm)
35
35
OIP3 (dBm)
3V
4V
5V
35
30
30
30
25
3V
4V
5V
25
25
3V
4V
5V
20
75
90
105
120
135
150
165 180
I
ds
(mA)
20
75
90
105
120
135
150
165 180
I
ds
(mA)
20
75
90
105
120
135
150
165
180
I
ds
(mA)
Figure 8. OIP3 vs. I
ds
and V
ds
at 900 MHz.
Figure 9. OIP3 vs. I
ds
and V
ds
at 2 GHz.
Figure 10. OIP3 vs. I
ds
and V
ds
at 3.9 GHz.
17
16
15
17
16
15
12
10
8
GAIN (dB)
14
13
12
11
10
75
90
105
120
135
150
165 180
I
ds
(mA)
3V
4V
5V
GAIN (dB)
14
13
12
11
10
75
90
105
120
135
150
165 180
I
ds
(mA)
3V
4V
5V
GAIN (dB)
6
4
2
0
3V
4V
5V
75
90
105
120
135
150
165
180
I
ds
(mA)
Figure 11. Small Signal Gain vs. I
ds
and V
ds
at 900 MHz.
30
Figure 12. Small Signal Gain vs. I
ds
and V
ds
at 2 GHz.
30
Figure 13. Small Signal Gain vs. I
ds
and V
ds
at 3.9 GHz.
30
25
25
25
P1dB (dBM)
P1dB (dBM)
20
20
P1dB (dBM)
3V
4V
5V
20
15
3V
4V
5V
15
15
3V
4V
5V
10
75
90
105
120
135
150
165 180
I
dq
(mA)
10
75
90
105
120
135
150
165 180
I
dq
(mA)
10
75
90
105
120
135
150
165
180
I
dq
(mA)
Figure 14. P1dB vs. I
dq
and V
ds
at 900 MHz.
Note:
Bias current for the above charts are quiescent
conditions. Actual level may increase or
decrease depending on amount of RF drive. The
objective of load pull is to optimize OIP3 and
therefore may trade-off Small Signal Gain, P1dB
and VSWR.
Figure 15. P1dB vs. I
dq
and V
ds
at 2 GHz.
Figure 16. P1dB vs. I
dq
and V
ds
at 3.9 GHz.
5
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