MC14557B
1-to-64 Bit Variable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or
negative edge clocking capability.
The device can be effectively used for variable digital delay lines or
simply to implement odd length shift registers.
•
1−64 Bit Programmable Length
•
Q and Q Serial Buffered Outputs
•
Asynchronous Master Reset
•
All Inputs Buffered
•
No Limit On Clock Rise and Fall Times
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Capable of Driving Two Low−power TTL Loads or one Low−power
Schottky TTL Load Over the Rated Temperature Range
•
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 2)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5
to +18.0
−0.5
to V
DD
+ 0.5
±10
500
−55
to +125
−65
to +150
260
Unit
V
V
mA
mW
°C
°C
°C
1
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MARKING DIAGRAMS
16
16
1
PDIP−16
P SUFFIX
CASE 648
1
MC14557BCP
AWLYYWWG
16
14557B
AWLYYWWG
1
SO−16 WB
DW SUFFIX
CASE 751G
1
16
MC14557B
ALYWG
SOEIAJ−16
F SUFFIX
CASE 966
A
WL, L
YY, Y
WW, W
G
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. V
in
and V
out
should be constrained to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/°C From 65°C To 125°C
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
June, 2011
−
Rev. 6
1
Publication Order Number:
MC14557B/D
MC14557B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
5.0
10
15
5.0
10
15
15
−
5.0
10
15
5.0
10
15
−
55°C
25°C
125°C
Symbol
V
OL
Characteristic
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
Typ
(Note 3)
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±
0.00001
5.0
0.010
0.020
0.030
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
“0” Level
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±
0.1
−
5.0
10
20
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±
0.1
7.5
5.0
10
20
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±
1.0
−
150
300
600
mAdc
pF
mAdc
V
OH
V
in
= 0 or V
DD
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 4, 5)
(Dynamic plus Quiescent, Per Package)
(C
L
= 50 pF on all outputs, all buffers switching)
“1” Level
Vdc
V
IL
“0” Level
Vdc
V
IH
“1” Level
Vdc
I
OH
Source
mAdc
I
OL
Sink
I
in
C
in
I
DD
I
T
I
T
= (1.75
mA/kHz)
f + I
DD
I
T
= (3.50
mA/kHz)
f + I
DD
I
T
= (5.25
mA/kHz)
f + I
DD
mAdc
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25°C.
5. To calculate total supply current at loads other than 50 pF: I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk where: I
T
is in
mA
(per package), C
L
in pF,
V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
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MC14557B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(Note 6) (C
L
= 50 pF, T
A
= 25°C)
Symbol
Characteristic
V
DD
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
−
−
−
160
80
70
Min
−
−
−
−
−
−
−
−
−
200
100
75
300
140
100
−
−
−
700
290
145
400
165
60
200
100
10
400
185
85
Typ
(Note 7)
100
50
40
300
130
90
300
130
95
95
45
35
150
70
50
3.0
7.5
13.0
350
130
85
45
5
0
–150
–60
–50
50
25
22
No Limit
−
−
−
80
40
35
15
5
4
−
−
−
ms
Max
200
100
80
600
260
180
ns
600
260
190
−
−
−
−
−
−
1.7
5.0
6.7
−
−
−
−
−
−
ns
−
−
−
−
−
−
−
ns
Unit
ns
t
TLH
,
t
THL
Rise and Fall Time, Q or Q Output
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
PLH
,
t
PHL
Propagation Delay, Clock or CE to Q or Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
Propagation Delay, Reset to Q or Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 70 ns
Pulse Width, Clock
ns
t
PLH
,
t
PHL
t
WH(cl)
t
WH(rst)
Pulse Width, Reset
ns
f
cl
Clock Frequency (50% Duty Cycle)
MHz
t
su
Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = V
SS
(Register Length = 1)
Best case condition: L32 = V
DD
, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
t
h
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = V
SS
(Register Length = 1)
Worst case condition: L32 = V
DD
, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
t
r
,
t
f
t
r
,
t
f
t
rem
Rise and Fall Time, Clock
ns
Rise and Fall Time, Reset or CE
Removal Time, Reset to Clock or CE
ns
6. The formulas given are for the typical characteristics only at 25°C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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