NBSG14
2.5 V/3.3 V SiGe Differential
1:4 Clock/Data Driver with
RSECL* Outputs
*Reduced Swing ECL
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Description
The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for
ultra-low skew and jitter.
Inputs incorporate internal 50
W
termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
All outputs loaded with 50
W
to V
CC
− 2 V.
Features
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAMS*
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
= 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak-to-Peak Output),
Differential Output
50
W
Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
These are Pb-Free Devices
A
L
Y
W
G
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 17
ÇÇÇ
ÇÇÇ
ÇÇÇ
16
1
SG
14
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
NBSG14/D
NBSG14
V
EE
16
VTCLK
CLK
CLK
VTCLK
Q0
15
Q0
14
V
CC
13
Exposed Pad (EP)
1
2
NBSG14
3
4
12 Q1
11 Q1
10 Q2
9
Q2
5
V
EE
6
Q3
7
Q3
8
V
CC
Figure 1. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
VTCLK
CLK
I/O
−
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
−
−
RSECL Output
RSECL Output
−
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
−
Description
Internal 50
W
Termination pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
3
CLK
Noninverted Differential Input. Internal 75 kW to VEE.
4
5, 16
6
7
8, 13
9
10
11
12
14
15
−
VTCLK
V
EE
Q3
Q3
V
CC
Q2
Q2
Q1
Q1
Q0
Q0
EP
Internal 50
W
Termination Pin. See Table 2.
Negative Supply Voltage. All V
EE
Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
Inverted Differential Output 3. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Noninverted Differential Output 3. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Positive Supply Voltage. All V
CC
Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
Inverted Differential Output 2. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Noninverted Differential Output 2. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Inverted Differential Output 1. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Noninverted Differential Output 1. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Inverted Differential Output 0. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
Noninverted Differential Output 0. Typically Terminated with 50
W
to V
TT
= V
CC
− 2 V
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat-sinking
conduit. The pad is not electrically connected to the die but may be electrically and thermally
connected to V
EE
on the PC board.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no signal
is applied then the device will be susceptible to self-oscillation.
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2
NBSG14
V
CC
Q3
Q3
VTCLK
36.5 KW
Q2
50
W
Q2
CLK
CLK
50
W
VTCLK
75 KW
75 KW
Q1
Q1
V
EE
Q0
Q0
Figure 2. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTCLK and VTCLK to V
CC
Connect VTCLK and VTCLK Together
Bias VTCLK and VTCLK Inputs within
Common Mode Range (V
IHCMR
)
Standard ECL Termination Techniques
An External Voltage (V
th
) should be Applied to
the Unused Differential Input. Nominal V
th
is
1.5 V for LVTTL and V
CC
/2 for LVCMOS Inputs.
This Voltage must be within the V
th
Specification.
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (CLK, CLK)
Internal Input Pullup Resistor (CLK)
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
Pb-Free
Oxygen Index: 28 to 34
Value
75 kW
36.5 kW
> 2 kV
> 100 V
Level 1
UL 94 V−0 @ 0.125 in
158
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NBSG14
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
IN
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage |CLK−CLK|
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
(Note 2)
Thermal Resistance (Junction-to-Case)
Wave Solder (Pb-Free)
0 lfpm
500 lfpm
2S2P (Note 2)
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
CC
− V
EE
≥
2.8 V
V
CC
− V
EE
< 2.8 V
Static
Surge
Continuous
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
−V
EE
|
45
80
25
50
−40 to +70
−40 to +85
−65 to +150
41.6
35.2
4.0
265
Unit
V
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG14
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
(V
CC
= 2.5 V; V
EE
= 0 V) (Note 3)
−40°C
Symbol
Characteristic
Min
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
POWER SUPPLY CURRENT
I
EE
Negative Power Supply Current
45
60
75
45
60
75
45
60
75
mA
RSPECL OUTPUTS
(Note 4)
V
OH
V
OUTPP
Output HIGH Voltage
Output Voltage Amplitude
1525
315
1575
405
1625
495
1550
315
1610
405
1650
495
1575
315
1635
405
1675
495
mV
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED
(Figures 5 & 7) (Note 5)
V
IH
V
IL
V
th
V
ISE
Input HIGH Voltage
Input LOW Voltage
Input Threshold Voltage Range
(Note 6)
Single-Ended Input Voltage
(V
IH
– V
IL
)
1200
0
950
150
V
CC
V
IH
−
150
V
CC
–
75
2600
1200
0
950
150
V
CC
V
IH
−
150
V
CC
–
75
2600
1200
0
950
150
V
CC
V
IH
−
150
V
CC
–
75
260
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 6 & 8) (Note 7)
V
IHD
V
ILD
V
ID
V
IHCMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage
(V
IHD
– V
ILD
)
Input HIGH Voltage Common Mode
Range (Note 8) (Figure 9)
Input HIGH Current (@V
IH
)
Input LOW Current (@V
IL
)
1200
0
75
1200
80
25
V
CC
V
IHD
−
75
2600
2500
150
100
1200
0
75
1200
80
25
V
CC
V
IHD
−
75
2600
2500
150
100
1200
0
75
1200
80
25
V
CC
V
IHD
−
75
2600
2500
150
100
mV
mV
mV
mV
mA
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
CC
.
4. All outputs loaded with 50
W
to V
CC
− 2.0 V.
5. V
th
, V
IH
, V
IL,
and V
ISE
parameters must be complied with simultaneously.
6. V
th
is applied to the complementary input when operating in single-ended mode. V
th
= (V
IH
− V
IL
) / 2.
7. V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
8. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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