M390S2858DT1-C7C datasheet, PDF

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M390S2858DT1-C7C: Description128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD; Categorystorage storage; File Size157KB，12 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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M390S2858DT1-C7C Overview

128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD

M390S2858DT1-C7C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	DIMM
package instruction	DIMM, DIMM168
Contacts	168
Reach Compliance Code	compli
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N168
memory density	9663676416 bi
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Humidity sensitivity level	1
Number of functions	1
Number of ports	1
Number of terminals	168
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM168
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.074 A
Maximum slew rate	5 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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M390S2858DT1

M390S2858DT1 SDRAM DIMM

PC133 Registered DIMM

128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD

GENERAL DESCRIPTION

The Samsung M390S2858DT1 is a 128M bit x 72 Synchro-

nous Dynamic RAM high density memory module. The Sam-

sung M390S2858DT1 consists of eighteen CMOS Stacked

128Mx4 bit Synchronous DRAMs in two TSOP-II 400mil pack-

ages, three 18-bits Drive ICs for input control signal, one PLL

in 24-pin TSSOP package for clock and one 2K EEPROM in 8-

pin TSSOP package for Serial Presence Detect on a 168-pin

glass-epoxy substrate. Two 0.22uF and one 0.0022uF decou-

pling capacitors are mounted on the printed circuit board in

parallel for each SDRAM. The M390S2858DT1 is a Dual In-

line Memory Module and is intented for mounting into 168-pin

edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies allows the same device to be useful for a variety of high

bandwidth, high performance memory system applications.

FEATURE

• Performance range

Part No.

M390S2858DT1-C7C

M390S2858DT1-C7A

•

Max Freq. (Speed)

133MHz(7.5ns @ CL=2)

133MHz (7.5ns @ CL=3)

Burst mode operation

Auto & self refresh capability (8192 Cycles/64ms)

LVTTL compatible inputs and outputs

Single 3.3V

0.3V power supply

MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4 , 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB :

Height (1,700mil),

double sided component

PIN CONFIGURATIONS (Front side/back side)

Front

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CB0

CB1

DQM0

Front

DQ18

DQ19

DQ20

REF

*CKE1

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

*CLK2

*WP

**SDA

**SCL

Back

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

Back

DQM5

CS1

RAS

BA0

A11

*CLK1

A12

CKE0

CS3

DQM6

DQM7

*A13

CB6

CB7

DQ48

DQ49

Back

29 DQM1 57

CS0

38 A10/AP 66

BA1

42 CLK0 70

CS2

46 DQM2 74

47 DQM3 75

CB2

CB3

55 DQ16 83

56 DQ17 84

86 DQ32

87 DQ33

88 DQ34

89 DQ35

91 DQ36

92 DQ37

93 DQ38

94 DQ39

95 DQ40

97 DQ41

98 DQ42

99 DQ43

100 DQ44

101 DQ45

102 V

103 DQ46

104 DQ47

105 CB4

106 CB5

107

108

109

110 V

111 CAS

112 DQM4

141 DQ50

142 DQ51

143 V

144 DQ52

145

146 *V

REF

147 REGE

148

149 DQ53

150 DQ54

151 DQ55

152

153 DQ56

154 DQ57

155 DQ58

156 DQ59

157 V

158 DQ60

159 DQ61

160 DQ62

161 DQ63

162

163 *CLK3

164

165 **SA0

166 **SA1

167 **SA2

168 V

PIN NAMES

Pin Name

A0 ~ A12

BA0 ~ BA1

DQ0 ~ DQ63

CB0 ~ CB7

CLK0

CKE0

CS0 ~ CS3

RAS

CAS

DQM0 ~ 7

REF

REGE

SDA

SCL

SA0 ~ 2

*WP

Function

Address input (Multiplexed)

Select bank

Data input/output

Check bit (Data-in/data-out)

Clock input

Clock enable input

Chip select input

Row address strobe

Colume address strobe

Write enable

DQM

Power supply (3.3V)

Ground

Power supply for reference

Serial data I/O

Serial clock

Address in EEPROM

Don′t use

No connection

Write protection

* These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 0.0 Jan. 2002

M390S2858DT1-C7C Related Products

	M390S2858DT1-C7C	M390S2858DT1-C7A	M390S2858DT1
Description	128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD	128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD	128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
Is it Rohs certified?	incompatible	incompatible	-
Maker	SAMSUNG	SAMSUNG	-
Parts packaging code	DIMM	DIMM	-
package instruction	DIMM, DIMM168	DIMM, DIMM168	-
Contacts	168	168	-
Reach Compliance Code	compli	compli	-
ECCN code	EAR99	EAR99	-
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	-
Maximum access time	5.4 ns	5.4 ns	-
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-
Maximum clock frequency (fCLK)	133 MHz	133 MHz	-
I/O type	COMMON	COMMON	-
JESD-30 code	R-XDMA-N168	R-XDMA-N168	-
memory density	9663676416 bi	9663676416 bi	-
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	-
memory width	72	72	-
Humidity sensitivity level	1	1	-
Number of functions	1	1	-
Number of ports	1	1	-
Number of terminals	168	168	-
word count	134217728 words	134217728 words	-
character code	128000000	128000000	-
Operating mode	SYNCHRONOUS	SYNCHRONOUS	-
Maximum operating temperature	70 °C	70 °C	-
organize	128MX72	128MX72	-
Output characteristics	3-STATE	3-STATE	-
Package body material	UNSPECIFIED	UNSPECIFIED	-
encapsulated code	DIMM	DIMM	-
Encapsulate equivalent code	DIMM168	DIMM168	-
Package shape	RECTANGULAR	RECTANGULAR	-
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	-
Peak Reflow Temperature (Celsius)	225	225	-
power supply	3.3 V	3.3 V	-
Certification status	Not Qualified	Not Qualified	-
refresh cycle	8192	8192	-
self refresh	YES	YES	-
Maximum standby current	0.074 A	0.074 A	-
Maximum slew rate	5 mA	4.46 mA	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	3 V	3 V	-
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-
surface mount	NO	NO	-
technology	CMOS	CMOS	-
Temperature level	COMMERCIAL	COMMERCIAL	-
Terminal form	NO LEAD	NO LEAD	-
Terminal pitch	1.27 mm	1.27 mm	-
Terminal location	DUAL	DUAL	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-

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