Crystal-to-LVPECL Clock Synthesizer
ICS843156I
DATA SHEET
General Description
The ICS843156I is a high frequency clock generator. The
ICS843156I uses an external 25MHz crystal to synthesize
156.25MHz clock. The ICS843156I has excellent cycle-to-cycle and
RMS period jitter performance.
The ICS843156I operates at full 3.3V and 2.5V, or mixed 3.3V/2.5V
operating supplies and is available in a fully RoHS compliant 32-lead
VFQFN package.
Features
•
•
•
•
•
•
•
•
Ten differential LVPECL outputs of 156.25MHz
Crystal oscillator interface designed for 18pF, 25MHz parallel
resonant crystal
Cycle-to-cycle jitter: 40ps (maximum)
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.39ps (typical)
Output Duty Cycle: 45% – 55%
Full 3.3V and 2.5V, or mixed 3.3V/2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Output Frequency Table
Crystal Frequency (MHz)
25
Feedback Divider
25
VCO Frequency (MHz)
625
Output Divider
÷4
Output Frequency (MHz)
156.25
Pin Assignment
TEST_CLK
BYPASS
nQA0
QA5
V
CCO
V
CCA
QA0
V
CC
32 31 30
29 28 27 26 25
XTAL_IN
XTAL_OUT
1
2
24 QA1
23 nQA1
22 QA2
V
CC
3
nQC1 4
QC1
nQC0
5
6
ICS843156I
V
EE
21 nQA2
20 QA3
19 nQA3
18 QA4
17 nQA4
QC0 7
V
CCO
8
9
nQB1
10 11 12 13 14 15 16
nQA5
nQB0
V
CCO
QB1
QB0
V
EE
Block Diagram
BYPASS
Pulldown
TEST_CLK
XTAL_IN
Pulldown
25MHz
1
6
QA[0:5]
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm EPad
K Package
Top View
OSC
XTAL_OUT
÷4
Phase
Detector
VCO
625MHz
0
nQA[0:5]
2
QB[0:1]
nQB[0:1]
÷4
÷25
÷4
2
QC[0:1]
nQC[0:1]
ICS843156AKI REVISION B NOVEMBER 28, 2012
1
©2012 Integrated Device Technology, Inc.
ICS843156I Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1,
2
3, 32
4, 5
6, 7
8, 16, 25
9, 10
11, 12
13, 30
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28
Name
XTAL_IN
XTAL_OUT
V
CC
nQC1, QC1
nQC0, QC0
V
CCO
nQB1, QB1
nQB0, QB0
V
EE
nQA5, QA5
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
V
CCA
BYPASS
Input
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Power
Type
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Core supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
A HIGH on BYPASS signal allows TEST_CLK to propagate to output
dividers and bypass the PLL. a LOW on BYPASS signal allows VCO
frequency to propagate to the output dividers. See Table 3.
LVCMOS/LVTTL interface levels.
Single-ended input test clock. LVCMOS interface levels.
29
Input
Pulldown
31
TEST_CLK
Input
Pulldown
NOTE:
Pulldown
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Function Table
Table 3. Bypass Function Table
Input
BYPASS
0
1
Device Configuration
PLL Mode
Bypass the PLL
ICS843156AKI REVISION B NOVEMBER 28, 2012
2
©2012 Integrated Device Technology, Inc.
ICS843156I Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
CC
-0.5V to V
CC
+ 0.5V
50mA
100mA
37C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.33
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
179
33
Units
V
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
CC
– 0.23
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
CC
2.625
168
23
Units
V
V
V
mA
mA
Table 4C. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3
Test Conditions
Minimum
3.135
V
CC
– 0.33
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
CC
2.625
164
33
Units
V
V
V
mA
mA
ICS843156AKI REVISION B NOVEMBER 28, 2012
©2012 Integrated Device Technology, Inc.
ICS843156I Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Table 4D. LVCMOS/LVTTL DC Characteristics,
T
A
=
-40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
BYPASS,
TEST_CLK
BYPASS,
TEST_CLK
V
CC
= 3.3V
V
CC
= 2.5V
Input High Current
Input Low Current
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 4E. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
Output Low Voltage
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
Table 4F. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
CCO
= 2.5V ± 5%,V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
Output Low Voltage
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.5
1.0
Units
V
V
V
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
ICS843156AKI REVISION B NOVEMBER 28, 2012
4
©2012 Integrated Device Technology, Inc.
ICS843156I Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 6A. AC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
f
OUT
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
t
LOCK
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter, (Random);
NOTE 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
156.25MHz, Integration Range:
1.875MHz - 20MHz
20% to 80%
200
45
0.39
700
55
100
Test Conditions
Minimum
Typical
156.25
40
Maximum
Units
MHz
ps
ps
ps
%
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Refer to phase noise plot.
Table 6B. AC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
f
OUT
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
t
LOCK
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter, (Random)
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
156.25MHz, Integration Range:
1.875MHz - 20MHz
20% to 80%
200
45
0.49
700
55
100
Test Conditions
Minimum
Typical
156.25
35
Maximum
Units
MHz
ps
ps
ps
%
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
Table 6C. AC Characteristics,
V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
-40°C to 85°C
Symbol
f
OUT
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
t
LOCK
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter, (Random)
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
156.25MHz, Integration Range:
1.875MHz - 20MHz
20% to 80%
200
45
0.40
700
55
100
Test Conditions
Minimum
Typical
156.25
40
Maximum
Units
MHz
ps
ps
ps
%
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
ICS843156AKI REVISION B NOVEMBER 28, 2012
5
©2012 Integrated Device Technology, Inc.
京公网安备 11010802033920号
EEWORLD
