SY89873LMG datasheet, PDF - EEWORLD Datasheet

SY89873LMG: DescriptionClock Fanout Buffer 3-OUT 1-IN 1:1/1:2 16-Pin QFN EP Tube; File Size282KB，11 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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SY89873LMG Overview

Clock Fanout Buffer 3-OUT 1-IN 1:1/1:2 16-Pin QFN EP Tube

SY89873LMG Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.39.00.01
Type	Fanout Buffer
Fanout	1:1/1:2
Number of Outputs per Chip	3
Maximum Propagation Delay Time @ Maximum CL (ns)	0.8@3V to 3.6V
Absolute Propagation Delay Time (ns)	0.8
Input Logic Level	LVDS\|LVPECL\|HSTL\|CML
Output Logic Level	LVDS
Minimum Operating Supply Voltage (V)	3
Typical Operating Supply Voltage (V)	3.3
Maximum Operating Supply Voltage (V)	3.6
Maximum Quiescent Current (mA)	115
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	85
Supplier Temperature Grade	Industrial
Packaging	Tube
Pin Count	16
Standard Package Name	QFN
Supplier Package	QFN EP
Mounting	Surface Mount
Package Height	0.85(Max)
Package Length	3
Package Width	3
PCB changed	16
Lead Shape	No Lead

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Micrel, Inc.

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

PROGRAMMABLE CLOCK DIVIDER

FANOUT BUFFER W/ INTERNAL TERMINATION

Precision Edge

SY89873L

Precision Edge

SY89873L

FEATURES

Guaranteed AC performance

• > 2.0GHz f

MAX

output toggle

• > 3.0GHz f

MAX

input

• < 800ps t

(matched-delay between banks)

• < 15ps within-device skew

• < 190ps rise/fall time

Low jitter design

• < 1ps

RMS

cycle-to-cycle jitter

Unique input termination and V

pin for DC-coupled

and AC-coupled inputs: any differential inputs

(LVPECL, LVDS, CML, HSTL)

Precision differential LVDS outputs

Matched delay: all outputs have matched delay,

independent of divider setting

TTL/CMOS inputs for select and reset/disable

Two LVDS output banks (matched delay)

• Bank A: Buffered copy of input clock (undivided)

• Bank B: Divided output (

16),

two copies

3.3V power supply

Wide operating temperature range: –40

C to +85

Available in 16-pin (3mm

3mm) QFN package

Precision Edge

DESCRIPTION

This 3.3V low-skew, low-jitter, precision LVDS output clock

divider accepts any high-speed differential clock input (AC- or

DC-coupled) CML, LVPECL, HSTL or LVDS and divides down

the frequency using a programmable divider ratio to create a

frequency-locked, lower speed version of the input clock. The

SY89873L includes two output banks. Bank A is an exact

copy of the input clock (pass through) with matched

propagation delay to Bank B, the divided output bank. Available

divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock

system this would provide availability of 311MHz, 155MHz,

77MHz or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination

design that allows access to the termination network through

a VT pin. This feature allows the device to easily interface to

all AC- or DC-coupled differential logic standards. A V

REF-AC

reference is included for AC-coupled applications.

The SY89873L is part of Micrel’s high-speed Precision

Edge

timing and distribution family. For 2.5V applications,

consider the SY89872U. For applications that require an

LVPECL output, consider the SY89871U.

The /RESET input asynchronously resets the divider outputs

(Bank B). In the pass-through function (Bank A) the /RESET

synchronously enables or disables the outputs on the next

falling edge of IN (rising edge of /N). Refer to the Timing

Diagram.

All support documentation can be found on Micrel’s web

site at: www.micrel.com.

APPLICATIONS

SONET/SDH line cards

Transponders

High-end, multiprocessor servers

FUNCTIONAL BLOCK DIAGRAM

/RESET

Enable

MUX

TYPICAL APPLICATION

622MHz/155.5MHz

SONET Clock Generator

/QA

REF-AC

/IN

50Ω

Divided

2, 4, 8

or 16

QB0

/QB0

QB1

/QB1

622MHz LVPECL

Clock In

/IN

OC-12 or

OC-3

Clock Gen

/QA

622MHz LVDS

Clock Out

155.5MHz LVDS

Clock Out

/QB

Bank B: 155.5MHz: For OC-3 line card

Set to divide-by-4

Bank A: 622MHz: For OC-12 line card

Set to pass-through

Decoder

United States Patent No. RE44,134

Precision Edge is a registered trademark of Micrel, Inc.

M9999-082407

hbwhelp@micrel.com or (408) 955-1690

Rev.: F

Amendment: /0

Issue Date: February 2007

SY89873LMG Related Products

	SY89873LMG	SY89873LMG-TR
Description	Clock Fanout Buffer 3-OUT 1-IN 1:1/1:2 16-Pin QFN EP Tube	Clock Fanout Buffer 3-OUT 1-IN 1:1/1:2 16-Pin QFN EP T/R
EU restricts the use of certain hazardous substances	Compliant	Compliant
ECCN (US)	EAR99	EAR99
Part Status	Active	Active
HTS	8542.39.00.01	8542.39.00.01
Type	Fanout Buffer	Fanout Buffer
Fanout	1:1/1:2	1:1/1:2
Number of Outputs per Chip	3	3
Maximum Propagation Delay Time @ Maximum CL (ns)	0.8@3V to 3.6V	0.8@3V to 3.6V
Absolute Propagation Delay Time (ns)	0.8	0.8
Input Logic Level	LVDS\|LVPECL\|HSTL\|CML	CML\|HSTL\|LVDS\|LVPECL
Output Logic Level	LVDS	LVDS
Minimum Operating Supply Voltage (V)	3	3
Typical Operating Supply Voltage (V)	3.3	3.3
Maximum Operating Supply Voltage (V)	3.6	3.6
Maximum Quiescent Current (mA)	115	115
Minimum Operating Temperature (°C)	-40	-40
Maximum Operating Temperature (°C)	85	85
Supplier Temperature Grade	Industrial	Industrial
Packaging	Tube	Tape and Reel
Pin Count	16	16
Standard Package Name	QFN	QFN
Supplier Package	QFN EP	QFN EP
Mounting	Surface Mount	Surface Mount
Package Height	0.85(Max)	0.85(Max)
Package Length	3	3
Package Width	3	3
PCB changed	16	16
Lead Shape	No Lead	No Lead

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