Micrel, Inc.
3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER
FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge
®
SY89873L
Precision Edge
®
SY89873L
FEATURES
Guaranteed AC performance
• > 2.0GHz f
MAX
output toggle
• > 3.0GHz f
MAX
input
• < 800ps t
PD
(matched-delay between banks)
• < 15ps within-device skew
• < 190ps rise/fall time
Low jitter design
• < 1ps
RMS
cycle-to-cycle jitter
Unique input termination and V
T
pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
Precision differential LVDS outputs
Matched delay: all outputs have matched delay,
independent of divider setting
TTL/CMOS inputs for select and reset/disable
Two LVDS output banks (matched delay)
• Bank A: Buffered copy of input clock (undivided)
• Bank B: Divided output (
÷
2,
÷
4,
÷
8,
÷
16),
two copies
3.3V power supply
Wide operating temperature range: –40
°
C to +85
°
C
Available in 16-pin (3mm
×
3mm) QFN package
Precision Edge
®
DESCRIPTION
This 3.3V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC- or
DC-coupled) CML, LVPECL, HSTL or LVDS and divides down
the frequency using a programmable divider ratio to create a
frequency-locked, lower speed version of the input clock. The
SY89873L includes two output banks. Bank A is an exact
copy of the input clock (pass through) with matched
propagation delay to Bank B, the divided output bank. Available
divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock
system this would provide availability of 311MHz, 155MHz,
77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a VT pin. This feature allows the device to easily interface to
all AC- or DC-coupled differential logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The SY89873L is part of Micrel’s high-speed Precision
Edge
®
timing and distribution family. For 2.5V applications,
consider the SY89872U. For applications that require an
LVPECL output, consider the SY89871U.
The /RESET input asynchronously resets the divider outputs
(Bank B). In the pass-through function (Bank A) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N). Refer to the Timing
Diagram.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
APPLICATIONS
SONET/SDH line cards
Transponders
High-end, multiprocessor servers
FUNCTIONAL BLOCK DIAGRAM
/RESET
Enable
FF
Enable
MUX
TYPICAL APPLICATION
622MHz/155.5MHz
SONET Clock Generator
QA
/QA
V
REF-AC
IN
V
T
/IN
50Ω
50Ω
Divided
by
2, 4, 8
or 16
QB0
/QB0
QB1
/QB1
622MHz LVPECL
IN
Clock In
/IN
OC-12 or
OC-3
Clock Gen
QA
/QA
622MHz LVDS
Clock Out
QB
155.5MHz LVDS
Clock Out
/QB
Bank B: 155.5MHz: For OC-3 line card
Set to divide-by-4
Bank A: 622MHz: For OC-12 line card
Set to pass-through
S0
Decoder
S1
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: F
Amendment: /0
Issue Date: February 2007
Micrel, Inc.
Precision Edge
®
SY89873L
PACKAGE/ORDERING INFORMATION
VCC
GND
S0
S1
Ordering Information
(1)
12
11
10
9
16
15
14
13
QB0
/QB0
QB1
/QB1
1
2
3
4
5
6
7
8
IN
VT
VREF-AC
/IN
Part Number
SY89873LMG
SY89873LMGTR
(2)
Package Operating
Type
Range
QFN-16
QFN-16
Industrial
Industrial
Package
Marking
873L with
Pb-Free bar line indicator
873L with
Pb-Free bar line indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
16-Pin QFN
PIN DESCRIPTION
Pin Number
1, 2, 3, 4
5, 6
7, 14
8
Pin Name
QB0, /QB0
QB1, /QB1
QA, /QA
VCC
/RESET,
/DISABLE
IN, /IN
VREF-AC
VT
GND
S0, S1
Pin Function
Differential Buffered Output Clocks: Divide by 2, 4, 8, 16.
LVDS compatible.
Differential Buffered Undivided Output Clock: LVDS compatible.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
TTL/CMOS Compatible Output Reset and Disable: Internal 25kΩ pull-up. Input threshold
is V
CC
/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In
addition, when LOW, Banks A and B will be disabled.
Differential Input: Internal 50Ω termination resistors to V
T
input.
See
“Input Interface Applications”
section.
Reference Voltage: Equal to V
CC
–1.4V (approx.), and used for AC-coupled applications.
Maximum sink/source current is 0.5mA. See
“Input Interface Applications”
section.
Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise,
see
“Input Interface Applications”
section.
Ground: Exposed pad is internally connected to GND and must be connected to a ground
plane for proper thermal operation.
Select Pins: LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH if left
unconnected (divided by 16 mode). S0 = LSB. Input threshold is V
CC
/2.
12, 9
10
11
13
16, 15
TRUTH TABLE
/RESET
/DISABLE
1
1
1
1
0
S1
0
0
1
1
X
S0
0
1
0
1
X
Bank A Output
Input Clock
Input Clock
Input Clock
Input Clock
QA = LOW, /QA = HIGH
(1)
Bank B Outputs
Input Clock
÷
2
Input Clock
÷
4
Input Clock
÷
8
Input Clock
÷
16
QB0 = LOW, /QB0 = HIGH
(2)
QB1 = LOW, /QB1 = HIGH
(2)
Notes:
1. On the next negative transition of the input signal.
2. Asynchronous Reset/Disable function. See
"Timing Diagram."
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
/RESET
/DISABLE
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
/QA
QA
VCC
2
Micrel, Inc.
Precision Edge
®
SY89873L
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .................................. –0.5V to +4.0V
Input Voltage (V
IN
) .................................. –0.5V to V
CC
+0.3
LVDS Output Current (I
OUT
) ....................................
±10mA
Input Current IN, /IN (I
IN
) ..........................................
±50mA
V
REF-AC
Input Sink/Source Current (I
VREF-AC
)
(3) ............
±2mA
Lead Temperature (soldering, 20 sec.) ..................... 260°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
CC
) ...................................... +3.3V
±10%
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Package Thermal Resistance
QFN
(θ
JA
)
Still-Air ............................................................. 60°C/W
500 lfpm ........................................................... 54°C/W
QFN
(Ψ
JB
)
(4)
Junction-to-Board ............................................ 38°C/W
DC ELECTRICAL CHARACTERISTICS
(5)
T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
|I
IN
|
V
REF-AC
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input High Voltage
IN, /IN
Input Low Voltage
IN, /IN
Input Voltage Swing
Differential Input Voltage Swing
Input Current
IN, /IN
Reference Voltage
Note 6
Note 6
Notes 6, 7
Notes 6, 7, 8
Note 6
Note 9
No load, Max V
CC
90
0.1
–0.3
0.1
0.2
45
V
CC
–1.525 V
CC
–1.425 V
CC
–1.325
Condition
Min
3.0
Typ
3.3
85
100
Max
3.6
115
110
V
CC
+0.3
V
CC
3.6
Units
V
mA
Ω
V
V
V
V
mA
V
Notes:
1. Permanent device damage may occur if
“Absolute Maximum Ratings”
are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to
“Absolute Maximum Ratings”
conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Due to the internal termination (see
“Input Buffer Structure”
) the input current depends on the applied voltages at IN, /IN and V
T
inputs. Do not apply a
combination of voltages that causes the input current to exceed the maximum limit!
7. See
“Timing Diagram”
for V
IN
definition. V
IN
(max) is specified when V
T
is floating.
8. See Figures 1c and 1d for V
DIFF
definition.
9. Operating using V
IN
is limited to AC-coupled PECL or CML applications only. Connect directly to V
T
pin.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89873L
LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS
(10)
V
CC
= 3.3V
±10%;
T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
V
OUT
V
OH
V
OL
V
OCM
V
OCM
Parameter
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
Condition
Notes 11, 12
Note 11
Note 11
Note 11
0.925
1.125
–50
1.275
50
Min
250
Typ
350
Max
450
1.475
Units
mV
V
V
V
mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(10)
V
CC
= 3.3V
±10%;
T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
–125
Condition
Min
2.0
0.8
20
–300
Typ
Max
Units
V
V
μA
μA
Notes:
10. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
11. Measured as per Figure 1a, 100 across Q and /Q outputs.
12. See Figure 1c.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY89873L
AC ELECTRICAL CHARACTERISTICS
(13)
V
CC
= 3.3V
±10%;
T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
f
MAX
Parameter
Maximum Output Toggle Frequency
(Bank A and Bank B)
Maximum Input Frequency
t
PD
t
SKEW
Differential Propagation Delay
(IN-to-Q)
Within-Device Skew (diff.)
(QB0-to-QB1)
Within-Device Skew (diff.)
(Bank A-to-Bank B)
Part-to-Part Skew (diff.)
t
rr
T
jitter
t
r
, t
f
Reset Recovery Time
Cycle-to-Cycle Jitter
Rise / Fall Time (20% to 80%)
Condition
Output Swing:
≥
200mV
Note 14
Input Swing < 400mV
Input Swing
≥
400mV
Note 15
Note 15
Note 15
Note 16
Note 17
60
110
600
1
190
Min
2.0
3.2
550
500
660
610
7
12
800
750
15
30
250
Typ
Max
Units
GHz
GHz
ps
ps
ps
ps
ps
ps
ps
RMS
ps
Notes:
13. Measured with 400mV input signal, 50% duty cycle. All outputs terminated with 100Ω between Q and /Q, unless otherwise stated.
14. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output
÷2, ÷4, ÷8, ÷16)
can accept an input frequency >3GHz,
while Bank A will be slew-rate limited.
15. Skew is measured between outputs under identical transitions.
16. See
“Timing Diagram.”
17. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
jitter_cc
=T
n
–T
n+1
, where T
is the time between rising edges of the output signal.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
5
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