Micrel, Inc.
2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS
SY89875U
Precision Edge
®
PROGRAMMABLE CLOCK DIVIDER AND 1:2
SY89875U
FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge
®
FEATURES
Integrated programmable clock divider and 1:2
fanout buffer
Guaranteed AC performance over temperature and
voltage:
• > 2.0GHz f
MAX
• < 200ps t
r
/t
f
• < 15ps within device skew
Low jitter design:
• < 10ps
PP
total jitter
• < 1ps
RMS
cycle-to-cycle jitter
Unique input termination and V
T
Pin for DC-coupled
and AC-coupled Inputs; CML, PECL, LVDS and
HSTL
LVDS compatible outputs
TTL/CMOS inputs for select and reset
Parallel programming capability
Programmable divider ratios of 1, 2, 4, 8 and 16
Low voltage operation 2.5V
Output disable function
–40°C to 85°C temperature range
Available in 16-pin (3mm x 3mm) MLF
®
package
DESCRIPTION
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS
or HSTL clock input signal and dividing down the frequency
using a programmable divider to create a lower speed
version of the input clock. Available divider ratios are 2, 4, 8
and 16, or straight pass-through.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a V
T
pin. This feature allows the device to
easily interface to different logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /IN).
TYPICAL PERFORMANCE
OC-12 to OC-3
Translator/Divider
APPLICATIONS
SONET/SDH line cards
Transponders
High-end, multiprocessor servers
FUNCTIONAL BLOCK DIAGRAM
S2
CML/LVPECL/LVDS
622MHz
Clock In
Divide-by-4
LVDS
155.5MHz
Clock Out
/RESET
Enable
FF
622MHz In
IN
Enable
MUX
Q0
/Q0
MUX
IN
50
V
T
50
/IN
Q1
/IN
Q0
9
9
Divided
by
2, 4, 8
or 16
/Q1
155.5MHz Out
S1
Decoder
S0
/Q0
V
REF_AC
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame
and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: August 2007
Micrel, Inc.
Precision Edge
®
SY89875U
PACKAGE/ORDERING INFORMATION
GND
VCC
S0
S1
Ordering Information(1)
Part Number
12
11
10
9
16
15
14
13
Package Operating
Type
Range
MLF-16
MLF-16
MLF-16
MLF-16
Industrial
Industrial
Industrial
Industrial
Package
Marking
875U
875U
875U with
Pb-Free bar line indicator
875U with
Pb-Free bar line indicator
Lead
Finish
Sn-Pb
Sn-Pb
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Q0
/Q0
Q1
/Q1
1
2
3
4
5
6
7
8
IN
VT
VREF-AC
/IN
SY89875UMI
SY89875UMITR
(2)
SY89875UMG
(3)
SY89875UMGTR
(2, 3)
NC
S2
/RESET
VCC
16-Pin MLF
®
(MLF-16)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number
12, 9
1, 2, 3, 4
16, 15, 5
6
8
Pin Name
IN, /IN
Q0, /Q0
Q1, /Q1
S0, S1, S2
NC
/RESET,
/DISABLE
Pin Function
Differential Input: Internal 50½ termination resistors to V
T
input. Flexible input accepts any
differential input. See
“Input Interface Applications”
section.
Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See
“Truth Table.”
Unused output pairs must be terminated with 100½ across the different pair.
Select Pins: See
“Truth Table.”
LVTTL/CMOS logic levels. Internal 25k½ pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is V
CC
/2.
No Connect.
LVTTL/CMOS Logic Levels: Internal 25k½ pull-up resistor. Logic HIGH if left unconnected.
Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable
function. The reset and disable function occurs on the next high-to-low clock input transition.
Input threshold is V
CC
/2.
Reference Voltage: Equal to V
CC
–1.4V (approx.). Used for AC-coupled applications only.
Decouple the V
REF–AC
pin with a 0.01µF capacitor. See
“Input Interface Applications”
section.
Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See
Figures 4a to 4f,
“Input Interface Applications”
section.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.
Ground. Exposed pad must be connected to the same potential as the GND pin.
10
11
7, 14
13
VREF-AC
VT
VCC
GND
Exposed
TRUTH TABLE
/RESET
(1)
1
1
1
1
1
0
(1)
Note 1.
S2
0
1
1
1
1
X
S1
X
0
0
1
1
X
S0
X
0
1
0
1
X
Outputs
Reference Clock (pass through)
Reference Clock ÷2
Reference Clock ÷4
Reference Clock ÷8
Reference Clock ÷16
Q = LOW, /Q = HIGH
Clock Disable
Reset/Disable function is asserted on the next clock input
(IN, /IN) high-to-low transition.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY89875U
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) ................................... –0.5V to +4.0V
Input Voltage (V
IN
) ................................... –0.5V to V
CC
+0.3
ECL Output Current (I
OUT
)
Continuous .......................................................... 50mA
Surge .................................................................100mA
Input Current IN, /IN (I
IN
) ......................................... ±50mA
V
T
Current (I
VT
) ...................................................... ±100mA
V
REF-AC
Sink/Source Current (I
VREF-AC
),
Note 3 ......
±2mA
Lead Temperature (soldering 20 sec.) ...................... 260°C
Storage Temperature (T
S
) ........................ –65°C to +150°C
Note 1.
Operating Ratings
(Note 2)
Supply Voltage (V
CC
) ......................................... +2.5V ±5%
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Package Thermal Resistance
MLF
®
(θ
JA
)
Still-Air ............................................................. 60°C/W
500lfpm ........................................................... 54°C/W
MLF
®
(ψ
JB
),
Note 4
Junction-to-Board ............................................ 32°C/W
Note 2.
Note 3.
Note 4.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng
conditions for extended periods may affect device reliability.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Due to the limited drive capability use for input of the same package only.
Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the pcb.
DC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
|I
IN
|
V
REF–AC
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input High Voltage (IN, /IN)
Input Low Voltage (IN, /IN)
Input Voltage Swing
Differential Input Voltage Swing
Input Current (IN, /IN)
Reference Voltage
Condition
Min
2.375
Typ
Max
2.625
Units
V
mA
½
V
V
V
V
mA
V
No load, max. V
CC
90
Note 3
Note 3
Note 4
Note 5
Note 3
Note 6
0.1
–0.3
0.1
0.2
–
70
100
–
–
–
–
–
95
110
V
CC
+0.3
V
IH
–0.1
V
CC
–
45
V
CC
–1.525 V
CC
–1.425 V
CC
–1.325
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
Due to the internal termination (see Figure 2a) the input current depends on the applied voltages at IN, /IN and V
T
inputs. Do not apply a combination
of voltages that causes the input current to exceed the maximum limit!
See
“Timing Diagram”
for V
IN
definition. V
IN
(Max) is specified when V
T
is floating.
See
“Typical Operating Characteristics”
section for V
DIFF
definition.
Operating using V
IN
is limited to AC-coupled PECL or CML applications only. Connect directly to V
T
pin.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89875U
LVDS DC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
V
CC
= 2.5V ±5%; T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
V
OUT
V
OH
V
OL
V
OCM
∆V
OCM
Note 1.
Note 2.
Note 3.
Note 4.
Parameter
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
Condition
Note 3, 4
Note 3
Note 3
Note 4
Min
250
Typ
350
Max
400
1.475
Units
mV
V
V
0.925
1.125
–50
1.375
50
V
mV
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
Measured as per Figure 2a, 100½ across Q and /Q outputs.
Measured as per Figure 2b.
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
V
CC
= 2.5V ±5%; T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Note 1.
Note 2.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Condition
Min
2.0
Typ
Max
Units
V
0.8
–125
20
–300
V
µA
µA
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY89875U
AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
V
CC
= 2.5V ±5%; T
A
= –40°C to +85°C; Unless otherwise stated.
Symbol
f
MAX
t
PD
t
SKEW
t
RR
t
JITTER
t
r
,t
f
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Parameter
Maximum Input Frequency
Differential Propagation Delay
IN to Q
Within-Device Skew (diff.)
Part-to-Part Skew (diff.)
Reset Recovery Time
Cycle-to-Cycle Jitter
Total Jitter
Rise/Fall Time (20% to 80%)
Condition
Output Swing ž 200mV
Input Swing < 400mV
Input Swing ž 400mV
Note 3
Note 3
Note 4
Note 5
Note 6
Min
2.0
590
540
Typ
2.5
690
690
5
Max
Units
GHz
870
820
15
280
ps
ps
ps
ps
ps
600
1
10
70
120
200
ps
RMS
ps
PP
ps
Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 100½ across each output pair, unless otherwise stated.
Specification for packaged product only.
Skew is measured between outputs under identical transitions.
See “Timing
Diagram.”
Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
jitter_cc
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
Total jitter definition: with an ideal clock input of frequency - f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than
the specified peak-to-peak jitter value.
TIMING DIAGRAM
/RESET
V
CC/2
t
RR
IN
V
ID
/IN
V
IN
Swing
/Q
V
OUT
Swing
Q
t
PD
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
5
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