K7R323682M
K7R321882M
K7R320982M
K7R320882M
Document Title
Preliminary
1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDR
TM
II b2 SRAM
1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR
TM
II b2 SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1.
2.
3.
4.
5.
6.
Pin name change from DLL to Doff.
Vddq range change from 1.5V to 1.5V~1.8V.
Update JTAG test conditions.
Reserved pin for high density name change from NC to Vss/SA
Delete AC test condition about Clock Input timing Reference Level
Delete clock description on page 2 and add HSTL I/O comment
Draft Date
June, 30 2001
Dec. 5 2001
Remark
Advance
Preliminary
0.2
1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
1.
2.
3.
4.
5.
1.
2.
3.
4.
Add 4Mx9 Organization.
Add -FC25 part (Part Number, Idd, AC Characteristics)
Add AC electrical characteristics.
Change AC timing characteristics.
Change DC electrical characteristics(I
SB1
)
Change the data Setup/Hold time.
Change the Access Time.(tCHQV, tCHQX, etc.)
Change the Clock Cycle Time.(MAX value of tKHKH)
Change the JTAG instruction coding.
July, 29. 2002
Preliminary
0.3
Sep. 6. 2002
Preliminary
0.4
Oct. 7. 2002
Preliminary
0.5
1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
1. Change the JTAG Block diagram
Dec. 16, 2002
Preliminary
0.6
Dec. 26, 2002
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Dec. 2002
Rev 0.6
K7R323682M
K7R321882M
K7R320982M
K7R320882M
Preliminary
1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDR
TM
II b2 SRAM
1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR
TM
II b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Separate independent read and write data ports
with concurrent read and write operation
• HSTL I/O
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x9, x18, x36) and nybble(x8) write function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impenance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
Organization
Part
Number
K7R323682M-FC25
X36
K7R323682M-FC20
K7R323682M-FC16
K7R323682M-FC13
K7R321882M-FC25
X18
K7R321882M-FC20
K7R321882M-FC16
K7R321882M-FC13
K7R320982M-FC25
X9
K7R320982M-FC20
K7R320982M-FC16
K7R320982M-FC13
K7R320882M-FC25
X8
K7R320882M-FC20
K7R320882M-FC16
K7R320882M-FC13
Cycle
Time
4.0
5.0
6.0
7.5
4.0
5.0
6.0
7.5
4.0
5.0
6.0
7.5
4.0
5.0
6.0
7.5
Access
Time
0.45
0.45
0.50
0.50
0.45
0.45
0.50
0.50
0.45
0.45
0.50
0.50
0.45
0.45
0.50
0.50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
D(Data in)
DATA
REG
36 (or 18)
19
(or 20)
WRITE/READ DECODE
36 (or 18)
WRITE DRIVER
19 (or 20)
ADDRESS
ADD
REG
OUTPUT SELECT
R
W
BW
X
4(or 2)
CTRL
LOGIC
1Mx36
(2Mx18)
MEMORY
ARRAY
SENSE AMPS
OUTPUT REG
72
(or 36)
72
(or 36)
OUTPUT DRIVER
36 (or 18)
Q(Data Out)
CQ, CQ
(Echo Clock out)
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
Notes:
1. Numbers in ( ) are for x18 device, x8 and x9 device also the same with appropriate adjustments of depth and width.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung techno logy.
-2-
Dec. 2002
Rev 0.6
K7R323682M
K7R321882M
K7R320982M
K7R320882M
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
2
V
SS
/SA*
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
Preliminary
1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDR
TM
II b2 SRAM
K7R323682M(1Mx36)
5
BW
2
BW
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW
1
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
V
SS
/SA*
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
PIN CONFIGURATIONS
(TOP VIEW)
NC/SA*
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
Notes :
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 64Mb, 10A for 128Mb and 2A for 256Mb
.
2. BW
0
controls write to D0:D8, BW
1
controls write to D9:D17, BW
2
controls write to D18:D26 and BW
3
controls write to D27:D35.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-35
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
4A
8A
7B,7A,5A,5B
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,
8M,4N,8N
10R
11R
2R
1R
3A
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
1
NOTE
Q0-35
W
R
B W
0
, BW
1,
BW
2
, B W
3
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
Data Outputs
Write Control Pin,active when low
Read Control Pin,active when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
D D
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-3-
Dec. 2002
Rev 0.6
K7R323682M
K7R321882M
K7R320982M
K7R320882M
Preliminary
1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDR
TM
II b2 SRAM
2
3
SA
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7R321882M(2Mx18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
V
SS
/SA*
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
Notes:
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 64Mb and 2A for 128Mb.
2. BW
0
controls write to D0:D8 and BW
1
controls write to D9:D17.
PIN NAME
SYMBOL
K, K
C, C
CQ, C Q
Doff
SA
D0-17
Q0-17
W
R
B W
0
, BW
1
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9J,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
Data Outputs
Write Control Pin,active when low
Read Control Pin,active when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
1
NOTE
Notes:
1. C, C, K or K cannot be set to V
R E F
voltage.
2. When ZQ pin is directly connected to V
D D
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
Dec. 2002
Rev 0.6
K7R323682M
K7R321882M
K7R320982M
K7R320882M
Preliminary
1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDR
TM
II b2 SRAM
2
3
SA
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
NW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7R320882M(4Mx8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
V
SS
/SA*
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
Notes:
1. * Checked No Connect(NC) pin is reserved for higher density address, i.e. 2A for 72Mb.
2. NW
0
controls write to D0:D3 and NW
1
controls write to D4:D7.
PIN NAME
SYMBOL
K, K
C, C
CQ, C Q
Doff
SA
D0-7
Q0-7
W
R
NW
0
, NW
1
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
11M,11J,10E,11C,2D,2G,3L,2N
11L,10J,11E,11B,3E,3G,2L,3P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,11D
1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J
1K,2K,3K,10K,11K,9J,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N
10N,11N,1P,2P,9P,10P,11P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
Data Outputs
Write Control Pin,active when low
Read Control Pin,active when low
Nybble Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
2
1
NOTE
NC
No Connect
3
Notes:
1. C, C, K or K cannot be set to V
R E F
voltage.
2. When ZQ pin is directly connected to V
D D
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-5-
Dec. 2002
Rev 0.6
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