.
IBM0312804 IBM0312164
IBM0312404 IBM03124B4
128Mb Synchronous DRAM - Die Revision A
Features
• High Performance:
-75A,
CL=3
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
1
t
AC
Clock Access Time
2
133
7.5
—
5.4
-260,
CL=2
100
10
—
6
-360, -10,
Units
CL=3 CL=3
100
10
—
6
100
10
7
9
MHz
ns
ns
ns
•
•
•
•
•
•
•
•
•
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard or Low Power operation
4096 refresh cycles/64ms
1. Terminated load. See AC Characteristics on page 39.
2. Unterminated load. See AC Characteristics on page 39.
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1 (bank select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, full-page
• Random Column Address every CLK (1-N Rule)
• Single 3.3V
±0.3V
Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
2 High Stack TSOJ
Description
The IBM0312404, IBM0312804, and IBM0312164
are four-bank Synchronous DRAMs organized as
8Mbit x 4 I/O x 4 Bank, 4Mbit x 8 I/O x 4 Bank, and
2Mbit x 16 I/O x 4 Bank, respectively. IBM03124B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve high-
speed data transfer rates of up to 133MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 128Mbit single tran-
sistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (BS0, BS1) are
strobed with RAS. Eleven column addresses (A0-
A9, A11) plus bank select addresses and A10 are
strobed with CAS. Column address A11 is dropped
on the x8 device and column addresses A9 and A11
are dropped on the x16 device. Access to the lower
or upper DRAM in a stacked device is controlled by
CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A13
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 133MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous opera-
tion of both decks of a stacked device is allowed,
depending on the operation being done. Auto
Refresh (CBR), Self Refresh, and Low Power opera-
tion are supported.
33L8019.F45415
7/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 70
IBM0312804 IBM0312164
IBM0312404 IBM03124B4
128Mb Synchronous DRAM - Die Revision A
Pin Description
CLK
CKE
CS (CS0, CS1)
RAS
CAS
WE
BS1, BS0
A0 - A11
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
DQ0-DQ15
DQM, LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
—
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
Input/Output Functional Description
Symbol
CLK
CKE
CS, CS0,
CS1
RAS, CAS,
WE
BS0, BS1
Type
Input
Input
Polarity
Positive
Edge
Active High
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
Input
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the
Active Low command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
Active Low
—
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to
be executed by the SDRAM.
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,
CA11) when sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BS0 and BS1 are used to define which bank to precharge.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Input
Input
A0 - A11
Input
—
DQ0 - DQ15
Input-
Output
—
DQM
LDQM
UDQM
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high.
In x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
Active High
enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM
has a latency of zero and operates as a word mask by allowing input data to be written if it is low
but blocks the write operation if DQM is high.
—
—
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
V
DD
, V
SS
V
DDQ
V
SSQ
Supply
Supply
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
33L8019.F45415
7/99
Page 4 of 70
Analog electronics
京公网安备 11010802033920号
EEWORLD
