MM74HC125/MM74HC126 3-STATE Quad Buffers
September 1983
Revised January 2005
MM74HC125/MM74HC126
3-STATE Quad Buffers
General Description
The MM74HC125 and MM74HC126 are general purpose
3-STATE high speed non-inverting buffers utilizing
advanced silicon-gate CMOS technology. They have high
drive current outputs which enable high speed operation
even when driving large bus capacitances. These circuits
possess the low power dissipation of CMOS circuitry, yet
have speeds comparable to low power Schottky TTL cir-
cuits. Both circuits are capable of driving up to 15 low
power Schottky inputs.
The MM74HC125 require the 3-STATE control input C to
be taken high to put the output into the high impedance
condition, whereas the MM74HC126 require the control
input to be low to put the output into high impedance.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 13 ns
s
Wide operating voltage range: 2–6V
s
Low input current: 1
µ
A maximum
s
Low quiescent current: 80
µ
A maximum (74HC)
s
Fanout of 15 LS-TTL loads
Ordering Code:
Order Number
MM74HC125M
MM74HC125SJ
MM74HC125MTC
MM74HC125MTCX-NL
MM74HC125N
MM74HC126M
MM74HC126MX_NL
MM74HC126SJ
MM74HC126MTC
MM74HC126MTCX_NL
MM74HC126N
N14A
M14A
M14A
M14D
MTC14
MTC14
N14A
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)
Pb-Free package per JEDEC J-STD-020B.
© 2005 Fairchild Semiconductor Corporation
DS005308
www.fairchildsemi.com
MM74HC125/MM74HC126
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin
(I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
(Note 4)
V
CC
2.0V
4.5V
6.0V
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
6.0 mA
|I
OUT
|
≤
7.8 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
6.0 mA
|I
OUT
|
≤
7.8 mA
I
OZ
Maximum 3-STATE Output
Leakage Current
I
IN
I
CC
Maximum Input Current
Maximum Quiescent
Supply Current
V
IN
=
V
IH
or V
IL
V
OUT
=
V
CC
or GND
C
n
=
Disabled
V
IN
=
V
CC
or GND
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
6.0V
6.0V
4.5V
6.0V
6.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
Recommended Operating
Conditions
Min Max Units
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times (t
r
, t
f
)
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
2
0
6
V
CC
V
V
−
0.5 to
+
7.0V
−
1.5 to V
CC
+
1.5V
−
0.5 to V
CC
+
0.5V
±
20 mA
±
35 mA
±
70 mA
−
65
°
C to
+
150
°
C
600 mW
500 mW
−
40
+
85
°
C
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
Conditions
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.5
T
A
= −40
to 85°C T
A
= −40
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±5
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±10
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
±0.1
8.0
±1.0
80
±1.0
160
µA
µA
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=5.5V
and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current
(I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
www.fairchildsemi.com
MM74HC125/MM74HC126
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
45 pF, t
r
=
t
f
=
6 ns
Symbol
t
PHL
, t
PLH
t
PZH
t
PHZ
t
PZL
t
PLZ
Maximum
Propagation Delay Time
Maximum
Output Enable Time to HIGH Level
Maximum
Output Disable Time from HIGH Level
Maximum
Output Enable Time to LOW Level
Maximum
Output Disable Time from LOW Level
R
L
=
1 kΩ
C
L
=
5 pF
13
25
ns
R
L
=
1 kΩ
C
L
=
5 pF
R
L
=
1 kΩ
18
25
ns
17
25
ns
R
L
=
1 kΩ
13
25
ns
Parameter
Conditions
Typ
13
Guaranteed
Limit
18
Units
ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
V
CC
2.0V
4.5V
6.0V
t
PLH
, t
PHL
Maximum Propagation
Delay Time
t
PZH
, t
PZL
Maximum Output
Enable Time
t
PHZ
, t
PLZ
Maximum Output
Disable Time
t
PZL
, t
PZH
Maximum Output
Enable Time
t
TLH
, t
THL
Maximum Output
Rise and Fall Time
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance Outputs
Power Dissipation
Capacitance (Note 5)
(per gate)
Enabled
Disabled
2
T
A
=
25°C
Typ
40
14
12
35
14
12
25
14
12
25
14
12
35
15
13
30
7
6
5
15
45
6
100
20
17
130
26
22
125
25
21
125
25
21
140
28
24
60
12
10
10
20
T
A
= −40
to 85°C T
A
= −40
to 125°C
Guaranteed Limits
125
25
21
163
33
28
156
31
26
156
31
26
175
35
30
75
15
13
10
20
150
30
25
195
39
39
188
38
31
188
38
31
210
42
36
90
18
15
10
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
pF
t
PHL
, t
PLH
Maximum Propagation
Delay Time
C
L
=
150 pF
2.0V
4.5V
6.0V
R
L
=
1 kΩ
2.0V
4.5V
6.0V
R
L
=
1 kΩ
2.0V
4.5V
6.0V
C
L
=
150 pF
R
L
=
1 kΩ
C
L
=
50 pF
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
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4
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