SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test
Support)
March 1993
Revised August 2000
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advan-
tage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove
a board from the system and retain test access to the
remaining modules. Each SCANPSC110F Bridge supports
up to 3 local scan rings which can be accessed individually
or combined serially. Addressing is accomplished by load-
ing the instruction register with a value matching that of the
Slot inputs. Backplane and inter-board testing can easily
be accomplished by parking the local TAP Controllers in
one of the stable TAP Controller states via a Park instruc-
tion. The 32-bit TCK counter enables built in self test oper-
ations to be performed on one port while other scan chains
are simultaneously tested.
Features
s
True IEEE1149.1 hierarchical and multidrop addressable
capability
s
The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
s
3 IEEE 1149.1-compatible configurable local scan ports
s
Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
s
32-bit TCK counter
s
16-bit LFSR Signature Compactor
s
L4
s
local TAPs can be 3-stated via the OE input to allow an
alternate test master to take control of the local TAPs
Ordering Code:
Order Number
SCANPSC110FSC
Package Number
M28B
Package Description
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin
Names
TCK
B
TMS
B
TDI
B
TDO
B
TRST
S
(0,5)
OE
Description
Backplane Test Clock Input
Backplane Test Mode Select Input
Backplane Test Data Input
Backplane Test Data Output
Asynchronous Test Reset Input (Active LOW)
Address Select Port
Local Scan Port Output Enable (Active LOW)
TCK
L(1–3)
Local Port Test Clock Output
TMS
L(1–3)
Local Port Test Mode Select Output
TDI
L(1–3)
Local Port Test Data Input
TDO
L(1–3)
Local Port Test Data Output
© 2000 Fairchild Semiconductor Corporation
DS011570
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SCANPSC110F
TABLE 1. Glossary of Terms
LFSR
LSP
Local
Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test
data.
Local Scan Port. A four signal port that drives a “local” (i.e. non-backplane) scan chain.
(e.g., TCK
L1
, TMS
L1
, TDO
L1
, TDI
L1
)
Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANPSC110F Bridge Test
Access Port that drives them. The term “local” was adopted from the system test architecture that the
SCANPSC110F Bridge will most commonly be used in; namely, a system test backplane with a
SCANPSC110F Bridge on each card driving up to 3 “local” scan rings per card. (Each card can contain
multiple SCANPSC110Fs, with 3 local scan ports per SCANPSC110F.)
Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the state
of the local TAP controllers (the “local TAP controllers” refers to the TAP controllers of the scan compo-
nents that make up a local scan ring). Park is also used to describe the action of parking a LSP (transi-
tioning into one of the Parked LSP controller states). It is important to understand that when a LSP
controller is in one of the parked states, TMS
L
is held constant, thereby holding or “parking” the local
TAP controllers in a given state.
Test Access Port as defined by IEEE Std. 1149.1
Park/Unpark
TAP
Selected/Unselected
Selected and Unselected refers to the state of the SCANPSC110F Bridge Selection Controller. A
selected SCANPSC110F has been properly addressed and is ready to receive Level 2 protocol. Unse-
lected SCANPSC110Fs monitor the system test backplane, but do not accept Level 2 protocol (except
for the
GOTOWAIT
instruction). The data registers and LSPs of unselected SCANPSC110Fs are not
accessible from the system test master.
Active Scan Chain
The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a SCANPSC110F is selected with all of its LSPs parked, the active scan chain is the
current scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDI
B
→
the
current SCANPSC110F register
→
the local scan ring registers
→
a PAD bit
→
TDO
B
. Refer to Table 4
for Unparked configurations of the LSP network.
Level 1 is the protocol used to address a SCANPSC110F.
Level 2 is the protocol that is used once a SCANPSC110F is selected. Level 2 protocol is IEEE Std.
1149.1 compliant when an individual SCANPSC110F is selected.
A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates
the prop delay that would be added by the SCANPSC110F LSPN logic between TDI
Ln
and TDO
L(n+1)
or TDO
B
by buffering and synchronizing the TDI
L
inputs to the falling edge of TCK
B
, thus allowing data
to be scanned at higher frequencies without violating set-up and hold times.
Least Significant Bit, the right-most position in a register (bit 0)
Most Significant Bit, the left-most position in a register
Level 1 Protocol
Level 2 Protocol
PAD
LSB
MSB
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2
SCANPSC110F
TABLE 2. Detailed Pin Description Table
Name
TMS
B
I/O (Note 1)
TTL Input w/Pull-Up Resistor
Pin #
(SOIC & LCC)
10
Description
BACKPLANE TEST MODE SELECT:
Controls sequencing
through the TAP Controller of the SCANPSC110F Bridge. Also
controls sequencing of the TAPs which are on the three (3) local
scan chains.
BACKPLANE TEST DATA INPUT:
All backplane scan data is
supplied to the SCANPSC110F through this input pin.
BACKPLANE TEST DATA OUTPUT:
This output drives test data
from the SCANPSC110F and the local TAPs, back toward the scan
master controller.
TDI
B
TDO
B
TTL Input w/Pull-Up Resistor
3-STATEable,
32 mA/64 mA Drive,
Reduced-Swing,
Output
12
13
TCK
B
TTL Schmitt Trigger Input
11
TEST CLOCK INPUT FROM THE BACKPLANE:
This is the mas-
ter clock signal that controls all scan operations of the
SCANPSC110F and of the three (3) local scan ports.
TEST RESET:
An asynchronous reset signal (active LOW) which
initializes the SCANPSC110F logic.
SLOT IDENTIFICATION:
The configuration of these six (6) pins is
used to identify (assign a unique address to) each SCANPSC110F
on the system backplane.
OUTPUT ENABLE for the Local Scan Ports, active LOW.
When
HIGH, this active-LOW control signal 3-STATEs all three local scan
ports on the SCANPSC110F, to enable an alternate resource to
access one or more of the three (3) local scan chains.
TEST DATA OUTPUTS:
Individual output for each of the three (3)
local scan ports.
TRST
S
(0–5)
TTL Input w/Pull-Up Resistor
TTL Inputs
9
2, 3, 4,
5, 6, 7
OE
TTL Input
1
TDO
L(1–3)
3-STATEable,
24 mA/24 mA
Drive Outputs
TDI
L(1–3)
TTL Inputs w/Pull-Up
Resistors
TMS
L(1–3)
3-STATEable,
24 mA/24 mA
Drive Outputs
TCK
L(1–3)
3-STATEable,
24 mA/24 mA
Drive Output
V
CC
GND
Power Supply Voltage
Ground potential
15,19,
24
18, 23,
27
16, 20,
25
TEST DATA INPUTS:
Individual scan data input for each of the
three (3) local scan ports.
TEST MODE SELECT OUTPUTS:
Individual output for each of the
three (3) local scan ports. TMS
L
does
not
provide a pull-up resistor
(which is assumed to be present on a connected TMS input, per
the IEEE 1149.1 requirement)
LOCAL TEST CLOCK OUTPUTS:
Individual output for each of
the three (3) local scan ports. These are buffered versions of
TCK
B
.
Power supply pins, 5.0V
±
10%.
Power supply pins 0V.
17, 22,
26
8, 28
14, 21
Note 1:
All pins are active HIGH unless otherwise noted.
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SCANPSC110F
Overview of SCANPSC110F Bridge Functions
FIGURE 1. SCANPSC110F Bridge Architecture
SCANPSC110F BRIDGE ARCHITECTURE
Figure 1 shows the basic architecture of the
SCANPSC110F. The device’s major functional blocks are
illustrated here. The TAP Controller, a 16-state state
machine, is the central control for the device. The instruc-
tion register and various test data registers can be scanned
to exercise the various functions of the SCANPSC110F
(these registers behave as defined in IEEE Std. 1149.1).
The SCANPSC110F selection controller provides the func-
tionality that allows the 1149.1 protocol to be used in a
multi-drop environment. It primarily compares the address
input to the slot identification and enables the
SCANPSC110F for subsequent scan operations.
The Local Scan Port Network (LSPN) contains multiplexing
logic used to select different port configurations. The LSPN
control block contains the Local Scan Port Controllers
(LSPC) for each Local Scan Port (LSP
1
, LSP
2
, and LSP
3
).
This control block receives input from the SCANPSC110F
instruction register, mode register, and the TAP controller.
Each local port contains all four (4) boundary scan signals
needed to interface with the local TAPs.
SCANPSC110F BRIDGE STATE MACHINES
The SCANPSC110F is IEEE 1149.1-compatible, in that it
supports all required 1149.1 operations. In addition, it sup-
ports a higher level of protocol, (Level 1), that extends the
IEEE 1149.1 Std. to a multi-drop environment.
In multi-drop scan systems, a scan tester can select indi-
vidual SCANPSC110Fs for participation in upcoming scan
operations. SCANPSC110F “selection” is accomplished by
simultaneously scanning a device address out to multiple
SCANPSC110Fs. Through an on-chip address matching
process, only those SCANPSC110Fs whose statically-
assigned address matches the scanned-out address
become selected to receive further instructions from the
scan tester. SCANPSC110F selection is done using a
“Level-1” protocol, while follow-on instructions are sent to
selected SCANPSC110Fs by using a “Level-2” protocol.
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4
SCANPSC110F
Overview of SCANPSC110F Bridge Functions
(Continued)
FIGURE 2. SCANPSC110F Bridge State Machines
inserted into and removed from the SCANPSC110Fs over-
The SCANPSC110F contains three distinct but coupled
all scan chain.
state-machines (see Figure 2). The first of these is the
TAP-control state-machine, which is used to drive the
The SCANPSC110F selection state-machine performs the
SCANPSC110Fs scan ports in conformance with the
address matching which gives the SCANPSC110F its
1149.1 Standard (see Figure 17 of appendix). The second
multi-drop capability. That logic supports single-
is the SCANPSC110F-selection state-machine (Figure 3).
SCANPSC110F access, multi-cast, and broadcast. The
The third state-machine actually consists of three identical
SCANPSC110F-selection state-machine implements the
but independent state-machines (see Figure 4), one per
chip’s Level-1 protocol.
SCANPSC110F local scan port. Each of these scan port-
selection state-machines allows individual local ports to be
KEY
+ =
OR
&
=
AND
ADDR
=
6-bit address in the Instruction Register
SLOT
=
Static address in the SCANPSC110F Selection Controller
FIGURE 3. State Machine for SCANPSC110F Bridge Selection Controller
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