QL6325-7PT280C datasheet, PDF - EEWORLD Datasheet

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QL6325-7PT280C: DescriptionField Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 1.50 MM HEIGHT, 0.80 MM PITCH, MO-205, LFBGA-280; CategoryProgrammable logic devices Programmable logic; File Size471KB，38 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL6325-7PT280C Overview

Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 1.50 MM HEIGHT, 0.80 MM PITCH, MO-205, LFBGA-280

QL6325-7PT280C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	BGA
package instruction	LFBGA, BGA280,19X19,32
Contacts	280
Reach Compliance Code	compliant
Combined latency of CLB-Max	1.1716 ns
JESD-30 code	S-PBGA-B280
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	1536
Equivalent number of gates	320640
Number of entries	320
Number of logical units	1536
Output times	320
Number of terminals	280
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1536 CLBS, 320640 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA280,19X19,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5,2.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	17 mm
Base Number Matches	1

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QL6325 Eclipse Data Sheet

• • • • • •

Combining Performance, Density, and Embedded RAM

Device Highlights

Flexible Programmable Logic

•

.25

m, Five layer metal CMOS Process

•

2.5 V V

, 2.5 V/3.3 V Drive Capable I/O

•

1,536 Logic Cells

•

320,640 Max System Gates

•

Up to 313 I/O Pins

Advanced Clock Network

•

Nine Global Clock Networks:

•

One Dedicated

•

Eight Programmable

•

20 Quad-Net Networks: Five per Quadrant

•

16 I/O Controls: Two per I/O Bank

Embedded Dual Port SRAM

•

Twenty four 2,304-bit Dual Port High

Memory - Dual Port RAM

High Speed Logic Cells

321K Gates

Performance SRAM Blocks

•

55,300 RAM Bits

•

RAM/ROM/FIFO Wizard for Automatic

Configuration

•

Configurable and Cascadable

Memory - Dual Port RAM

Programmable I/O

•

High performance Enhanced I/O (EIO):

Figure 1: Eclipse Block Diagram

Less than 3 ns Tco

•

Programmable Slew Rate Control

•

Programmable I/O Standards:

•

LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

•

Eight Independent I/O Banks

•

Three Register Configurations: Input,

Output, and Output Enable

www.quicklogic.com

•

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