CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Static Electrical Specifications
CONDITIONS
-55
o
C, +25
o
C
PARAMETER
Quiescent Device Current
I
DD
V
O
(V)
-
-
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage Low-Level
(Note 1)
Output Voltage
High Level (Note 1)
Input Low Voltage
I
OL
0.4
0.5
I
OH
4.6
9.5
V
OL
-
-
V
OH
-
-
V
IL
0.5, 4.5
0.5, 9.5
Input High Voltage
V
IH
0.5, 4.5
0.5, 9.5
Input Leakage Current
I
IN
-
-
Three-State Output
Leakage Current
Input Capacitance (Note 1)
Output Capacitance (Note 1)
NOTE:
1. Guaranteed but not tested.
I
OUT
0, 5
0, 10
C
IN
C
OUT
-
-
V
IN
(V)
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
-
-
-
0, 5
0, 10
0, 5
0, 10
-
-
V
DD
(V)
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
MIN
-
-
0.75
1.80
-
-
-
-
4.9
9.9
-
-
3.5
7
-
-
-
-
-
-
MAX
500
500
-
-
-0.5
-1.0
0.1
0.1
-
-
1.5
3
-
-
±1
±1
±1
±1
10
15
LIMITS
+125
o
C
MIN
-
-
0.5
1.2
-
-
-
-
4.9
9.8
-
-
3.5
7
-
-
-
-
-
-
MAX
1000
1000
-
-
-0.35
-0.70
0.2
0.2
-
-
1.5
3
-
-
±5
±5
±10
±10
10
15
UNITS
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
2
Specifications CDP1854A/3, CDP1854AC/3
Operating Conditions
At T
A
= Full Package-Temperature Range. For maximum reliability, operating conditions should be selected
so that operation is always within the following ranges:
CONDITIONS
-55
o
C, +25
o
C
PARAMETER
DC Operating Voltage Range
Input Voltage Range
Baud Rate (Receive or Transmit)
V
DD
(V)
-
-
5
10
MIN
4
V
SS
-
-
MAX
10.5
V
DD
250
520
MIN
4
V
SS
-
-
LIMITS
+125
o
C
MAX
6.5
V
DD
215
430
UNITS
V
V
K bits/s
K bits/s
Dynamic Electrical Specifications
t
R
, t
F
= 15ns, V
IH
= V
DD
, V
IL
= V
SS
, C
L
= 100pF, (See Figure 1)
LIMITS
-55
o
C, +25
o
C
+125
o
C
MIN
MAX
UNITS
PARAMETER
TRANSMITTER TIMING - MODE 1
Clock Period
t
CC
V
DD
(V)
MIN
MAX
5
10
240
120
-
-
280
145
-
-
ns
ns
Pulse Width
Clock Low Level
t
CL
5
10
105
55
135
65
125
70
-
-
-
-
-
-
125
65
155
80
165
80
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Clock High Level
t
CH
5
10
TPB
t
TT
5
10
Propagation Delay Time
Clock to Data Start Bit
t
CD
5
10
-
-
-
-
-
-
425
205
315
155
335
160
-
-
-
-
-
-
485
235
380
185
390
190
ns
ns
ns
ns
ns
ns
TPB to THRE
t
TTH
5
10
Clock to THRE
t
CTH
5
10
3
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications
t
R
, t
F
= 15ns, V
IH
= V
DD
, V
IL
= V
SS
, C
L
= 100pF, (See Figure 2)
LIMITS
-55
o
C, +25
o
C
PARAMETER
RECEIVER TIMING - MODE 1
Clock Period
t
CC
5
10
Pulse Width
Clock Low Level
t
CL
5
10
Clock High Level
t
CH
5
10
TPB
t
TT
5
10
Setup Time
Data Start Bit to Clock
t
DC
5
10
Propagation Delay Time
TPB to DATA AVAILABLE
t
TDA
5
10
Clock to DATA AVAILABLE
t
CDA
5
10
Clock to Overrun Error
t
COE
5
10
Clock to Parity Error
t
CPE
5
10
Clock to Framing Error
t
CFE
5
10
-
-
-
-
-
-
-
-
-
-
295
150
305
150
305
150
305
150
280
145
-
-
-
-
-
-
-
-
-
-
340
170
355
170
330
175
330
175
330
165
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
105
65
-
-
120
70
-
-
ns
ns
105
55
135
65
125
70
-
-
-
-
-
-
125
65
155
80
165
80
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
240
120
-
-
280
145
-
-
ns
ns
V
DD
(V)
MIN
MAX
MIN
+125
o
C
MAX
UNITS
4
CDP1854A/3, CDP1854AC/3
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
t
CC
t
CH
T CLOCK
1
2
3
t
CL
4
5
6
7
14
15
16
1
2
t
CD
WRITE (TPB)
(NOTE 3)
t
TT
THRE
t
TTH
t
CD
SDO
1ST DATA BIT
t
CTH
3
4
NOTES:
1. The holding register is loaded on the trailing edge of TPB.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
TC
after the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + t
CD
later.
3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0
FIGURE 1. TRANSMITTER TIMING DIAGRAM - MODE 1
t
CC
t
CH
R CLOCK
t
DC
(NOTE 1)
SDI
t
CL
1
2
3
4
CLOCK 7 1/2
SAMPLE
5
6
7
16
1
2
CLOCK 7 1/2 LOAD
HOLDING REGISTER
3
4
5
6
7
8
9
START BIT
t
TDA
PARITY
STOP BIT 1
t
CDA
DA
READ
(NOTE 2)
t
TT
TPB
t
COE
OE
(NOTE 3)
PE
(NOTE 3)
t
CPE
t
CFE
FE
NOTES:
1. If a start bit occurs at a time less than t
DC
before a high-to-low transition of the clock, the start bit may not be recognized until the next
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the receiver holding register
by the time a new word is loaded into the receiver holding register, the OE signal will come true.
3. OE and PE share terminal 15 and are also available as two separate bits in the status register.
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