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CDP1854AC3

Description
1 CHANNEL(S), 200K bps, SERIAL COMM CONTROLLER, CDIP40
Categorysemiconductor    The embedded processor and controller   
File Size118KB,12 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
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CDP1854AC3 Overview

1 CHANNEL(S), 200K bps, SERIAL COMM CONTROLLER, CDIP40

TM
CDP1854A/3,
CDP1854AC/3
High Reliability CMOS Programmable Universal
Asynchronous Receiver/Transmitter (UART)
Description
The CDP1854A/3 and CDP1854AC/3 are high reliability
silicon gate CMOS Universal Asynchronous Receiver/Trans-
mitter (UART) circuits. They are designed to provide the
necessary formatting and control for interfacing between
serial and parallel data. For example, these UARTs can be
used to interface between a peripheral or terminal with serial
I/O ports and the 8-bit CDP1800-series microprocessor
parallel data bus system. The CDP1854A/3 is capable of full
duplex operation, i.e., simultaneous conversion of serial
input data to parallel output data and parallel input data to
serial output data.
The CDP1854A/3 UART can be programmed to operate in
one of two modes by using the mode control input. When the
mode input is high (MODE = 1), the CDP1854A/3 is directly
compatible with the CDP1800 series microprocessor system
without additional interface circuitry. When the mode input is
low (MODE = 0), the device is functionally compatible with
industry standard UARTs such as the TR1602A and
CDP6402. It is also pin compatible with these types, except
that pin 2 is used for the mode control input.
The CDP1854A/3 and the CDP1854AC/3 are functionally
identical. The CDP1854A/3 has a recommended operating
voltage range of 4V to 10.5V, and the CDP1854AC/3 has a
recommended operating voltage range of 4V to 6.5V.
March 1997
Features
• Two Operating Modes
- Mode 0 - Functionally Compatible with Industry
Types Such as the TR1602A and CDP6402
- Mode 1 - Interfaces Directly with CDP1800 Series
Microprocessors without Additional Components
• Full or Half-Duplex Operation
• Parity, Framing, and Overrun Error Detection
• Fully Programmable with Externally Selectable Word
Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and
1, 1-1/2, or 2 Stop Bits
Ordering Information
PACK-
AGE
SBDIP
TEMP.
RANGE
5V/200K
BAUD
10V/400K
BAUD
PKG.
NO.
-55
o
C to +125
o
C CDP1854ACD3 CDP1854ACD3 D40.6
Pinouts
CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 0)
TOP VIEW
VDD
1
MODE (V
SS
)
2
V
SS
3
RRD
4
R BUS 7
5
R BUS 6
6
R BUS 5
7
R BUS 4
8
R BUS 3
9
R BUS 2
10
R BUS 1
11
R BUS 0
12
PE
13
FE
14
OE
15
SFD
16
R CLOCK
17
DAR
18
DA
19
SDI
20
40
T CLOCK
39
EPE
38
WLS 1
37
WLS 2
36
SBS
35
PI
34
CRL
33
T BUS 7
32
T BUS 6
31
T BUS 5
30
T BUS 4
29
T BUS 3
28
T BUS 2
27
T BUS 1
26
T BUS 0
25
SD0
24
TSRE
23
THRL
22
THRE
21
MR
CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 1)
TOP VIEW
V
DD
1
MODE (V
DD
)
2
V
SS
3
CS2
4
R BUS 7
5
R BUS 6
6
R BUS 5
7
R BUS 4
8
R BUS 3
9
R BUS 2
10
R BUS 1
11
R BUS 0
12
INT
13
FE
14
PE/OE
15
RSEL
16
R CLOCK
17
TPB
18
DA
19
SDI
20
NC = NO CONNECT
40
T CLOCK
39
CTS
38
ES
37
PS1
36
NC
35
CS3
34
RD/WR
33
T BUS 7
32
T BUS 6
31
T BUS 5
30
T BUS 4
29
T BUS 3
28
T BUS 2
27
T BUS 1
26
T BUS 0
25
SD0
24
RTS
23
CS1
22
THRE
21
CLEAR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number
1715.2

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