5962-9325801V2A datasheet, PDF

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5962-9325801V2A: Description5962-9325801V2A amplifier basic information: 5962-9325801V2A is an OPERATIONAL AMPLIFIER from Analog Devices Inc. Commonly used packaging methods are QCCN, LCC20,.35SQ 5962-9325801V2A amplifier core information: The minimum operating temperature of the 5962-9325801V2A is -55 °C and the maximum operating temperature is 125 °C. Its peak reflow temperature is 220. Its maximum bias current at 25°C is: 0.6 µA. Its maximum average bias current is 0.6 µA. The maximum slew rate of the 5962-9325801V2A given by the manufacturer is 13 mA, while the minimum slew rate is 85 V/us. Its minimum voltage gain is 5000. When the op amp is used in closed loop, at a specified closed-loop gain (usually 1 or 2, 10, etc.), the frequency when the gain of 5962-9325801V2A becomes 0.707 times the low-frequency gain is 21000 kHz. The nominal supply voltage of 5962-9325801V2A is 5 V, and its corresponding nominal negative supply voltage is -5 V. The input offset voltage of 5962-9325801V2A is 500 µV (Input offset voltage: the compensation voltage added between the two input terminals to make the output terminal of the operational amplifier 0V (or close to 0V).) Related dimensions of 5962-9325801V2A: 5962-9325801V2A has 20 terminals. Its terminal position type is: QUAD. Terminal pitch is 1.27 mm. Total pins: 20 5962-9325801V2A amplifier additional information: 5962-9325801V2A adopts the VOLTAGE-FEEDBACK architecture. It does not belong to the low offset class of amplifiers. The frequency compensation status of 5962-9325801V2A is: YES. Its temperature grade is: MILITARY. 5962-9325801V2A does not comply with Rohs certification. It contains lead. The corresponding JESD-30 code is: S-CQCC-N20. The packaging code of 5962-9325801V2A is: QCCN. The materials used in the 5962-9325801V2A package are mostly CERAMIC, METAL-SEALED COFIRED. The package shape is SQUARE. The 5962-9325801V2A package pin format is: CHIP CARRIER. Its terminal forms are: NO LEAD.; CategoryAnalog mixed-signal IC Amplifier circuit; File Size100KB，12 Pages; ManufacturerADI; Websitehttps://www.analog.com; Alternative parts：5962-9325801V2A

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5962-9325801V2A Overview

5962-9325801V2A amplifier basic information:

5962-9325801V2A is an OPERATIONAL AMPLIFIER from Analog Devices Inc. Commonly used packaging methods are QCCN, LCC20,.35SQ

5962-9325801V2A amplifier core information:

The minimum operating temperature of the 5962-9325801V2A is -55 °C and the maximum operating temperature is 125 °C. Its peak reflow temperature is 220. Its maximum bias current at 25°C is: 0.6 µA. Its maximum average bias current is 0.6 µA.

The maximum slew rate of the 5962-9325801V2A given by the manufacturer is 13 mA, while the minimum slew rate is 85 V/us. Its minimum voltage gain is 5000. When the op amp is used in closed loop, at a specified closed-loop gain (usually 1 or 2, 10, etc.), the frequency when the gain of 5962-9325801V2A becomes 0.707 times the low-frequency gain is 21000 kHz.

The nominal supply voltage of 5962-9325801V2A is 5 V, and its corresponding nominal negative supply voltage is -5 V. The input offset voltage of 5962-9325801V2A is 500 µV (Input offset voltage: the compensation voltage added between the two input terminals to make the output terminal of the operational amplifier 0V (or close to 0V).)

Related dimensions of 5962-9325801V2A:

5962-9325801V2A has 20 terminals. Its terminal position type is: QUAD. Terminal pitch is 1.27 mm. Total pins: 20

5962-9325801V2A amplifier additional information:

5962-9325801V2A adopts the VOLTAGE-FEEDBACK architecture. It does not belong to the low offset class of amplifiers. The frequency compensation status of 5962-9325801V2A is: YES. Its temperature grade is: MILITARY. 5962-9325801V2A does not comply with Rohs certification.

It contains lead. The corresponding JESD-30 code is: S-CQCC-N20. The packaging code of 5962-9325801V2A is: QCCN. The materials used in the 5962-9325801V2A package are mostly CERAMIC, METAL-SEALED COFIRED. The package shape is SQUARE.

The 5962-9325801V2A package pin format is: CHIP CARRIER. Its terminal forms are: NO LEAD.

5962-9325801V2A Parametric

Parameter Name	Attribute value
Brand Name	Analog Devices Inc
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	ADI
Parts packaging code	QLCC
package instruction	QCCN, LCC20,.35SQ
Contacts	20
Reach Compliance Code	compliant
ECCN code	EAR99
Amplifier type	OPERATIONAL AMPLIFIER
Architecture	VOLTAGE-FEEDBACK
Maximum average bias current (IIB)	0.6 µA
Maximum bias current (IIB) at 25C	0.6 µA
Nominal Common Mode Rejection Ratio	80 dB
frequency compensation	YES
Maximum input offset voltage	500 µV
JESD-30 code	S-CQCC-N20
low-dissonance	NO
Negative supply voltage upper limit	-18 V
Nominal Negative Supply Voltage (Vsup)	-5 V
Number of functions	4
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Encapsulate equivalent code	LCC20,.35SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220
power supply	+-5/+-15 V
Certification status	Qualified
Filter level	MIL-PRF-38535 Class V
minimum slew rate	85 V/us
Maximum slew rate	13 mA
Supply voltage upper limit	18 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	BIPOLAR
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Nominal Uniform Gain Bandwidth	21000 kHz
Minimum voltage gain	5000
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Change to the supply current test, I

, in table I. Update boilerplate. - rrp

Add radiation hardness requirements. Add case outline D. Add table IIB. - rrp

Add footnote to the supply voltage test in section 1.3. Add footnote to the

supply current and power supply rejection ratio test in table I. Update

boilerplate. – rrp

Change to the post irradiation test limits in table I for I

, IIB, A

, and I

Removed accelerated aging and dose rate burnout provisions in

section 4. – rrp

Added subgroup 4 to table IIA under group E end-point for device class V. – gt

Drawing updated to reflect current requirements. - rrp

Delete footnote 2/ from section 1.3. Delete footnote 5/ from Table I.

These footnotes were incorrectly added under revision C. - ro

DATE (YR-MO-DA)

99-11-16

00-05-05

01-10-17

APPROVED

R. MONNIN

01-11-15

03-03-11

05-09-07

10-04-22

R. MONNIN

C. SAFFLE

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

RICK C. OFFICER

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

CHECKED BY

RAJESH R. PITHADIA

APPROVED BY

MICHAEL A. FRYE

DRAWING APPROVAL DATE

94-03-02

REVISION LEVEL

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

MICROCIRCUIT, LINEAR, RADIATION

HARDENED, PRECISION, HIGH SPEED, QUAD

OPERATIONAL AMPLIFIER, MONOLITHIC

SILICON

SIZE

CAGE CODE

AMSC N/A

67268

SHEET

1 OF 11

5962-93258

DSCC FORM 2233

APR 97

5962-E240-10

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 2.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

ambient operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for

device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 49 (see MIL-PRF-38535, appendix A).

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-93258

SHEET

5962-9325801V2A Related Products

	5962-9325801V2A	5962-9325801VCA
Description	Aerospace Quad High-Speed Precision Op Amp	IC QUAD OP-AMP, 500 uV OFFSET-MAX, 21 MHz BAND WIDTH, CDIP14, CERDIP-14, Operational Amplifier
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	ADI	ADI
Parts packaging code	QLCC	DIP
package instruction	QCCN, LCC20,.35SQ	DIP, DIP14,.3
Contacts	20	14
Reach Compliance Code	compliant	unknown
ECCN code	EAR99	EAR99
Amplifier type	OPERATIONAL AMPLIFIER	OPERATIONAL AMPLIFIER
Architecture	VOLTAGE-FEEDBACK	VOLTAGE-FEEDBACK
Maximum average bias current (IIB)	0.6 µA	0.6 µA
Maximum bias current (IIB) at 25C	0.6 µA	0.6 µA
Nominal Common Mode Rejection Ratio	80 dB	80 dB
frequency compensation	YES	YES
Maximum input offset voltage	500 µV	500 µV
JESD-30 code	S-CQCC-N20	R-GDIP-T14
low-dissonance	NO	NO
Negative supply voltage upper limit	-18 V	-18 V
Nominal Negative Supply Voltage (Vsup)	-5 V	-5 V
Number of functions	4	4
Number of terminals	20	14
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
encapsulated code	QCCN	DIP
Encapsulate equivalent code	LCC20,.35SQ	DIP14,.3
Package shape	SQUARE	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE
Peak Reflow Temperature (Celsius)	220	NOT SPECIFIED
power supply	+-5/+-15 V	+-5/+-15 V
Certification status	Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
minimum slew rate	85 V/us	85 V/us
Maximum slew rate	13 mA	13 mA
Supply voltage upper limit	18 V	18 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	NO
technology	BIPOLAR	BIPOLAR
Temperature level	MILITARY	MILITARY
Terminal form	NO LEAD	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm
Terminal location	QUAD	DUAL
Maximum time at peak reflow temperature	30	NOT SPECIFIED
Nominal Uniform Gain Bandwidth	21000 kHz	21000 kHz
Minimum voltage gain	5000	5000
Base Number Matches	1	1

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