82C84A datasheet, PDF - EEWORLD Datasheet

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82C84A: Description8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP18; Categorysemiconductor The embedded processor and controller; File Size585KB，13 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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82C84A Overview

8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP18

82C84A Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	18
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
Processing package description	ROHS COMPLIANT, Plastic, DIP-18
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	Rectangle
Package Size	IN-line
Terminal form	THROUGH-hole
Terminal spacing	2.54 mm
terminal coating	MATTE Tin
Terminal location	pair
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
Microprocessor type	PROC specific clock generator
Maximum FCLK output frequency	8 MHz
Rated master clock crystal frequency	25 mHz

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DATASHEET

82C84A

CMOS Clock Generator Driver

The Intersil 82C84A is a high performance CMOS Clock

Generator-driver which is designed to service the requirements

of both CMOS and NMOS microprocessors such as the

80C86, 80C88, 8086 and the 8088. The chip contains a crystal

controlled oscillator, a divide-by-three counter and complete

“Ready” synchronization and reset logic.

Static CMOS circuit design permits operation with an external

frequency source from DC to 25MHz. Crystal controlled

operation to 25MHz is guaranteed with the use of a parallel,

fundamental mode crystal and two small load capacitors.

All inputs (except X1 and RES) are TTL compatible over

temperature and voltage ranges.

Power consumption is a fraction of that of the equivalent

bipolar circuits. This speed-power characteristic of CMOS

permits the designer to custom tailor his system design with

respect to power and/or speed requirements.

FN2974

Rev 4.00

Sep 9, 2015

Features

• Generates the System Clock For CMOS or NMOS

Microprocessors

• Up to 25MHz Operation

• Uses a Parallel Mode Crystal Circuit or External

Frequency Source

• Provides Ready Synchronization

• Generates System Reset Output From Schmitt Trigger

Input

• TTL Compatible Inputs/Outputs

• Very Low Power Consumption

• Single 5V Power Supply

• Operating Temperature Ranges

- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

- M82C84A . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinouts

CSYNC

PCLK

AEN1

82C84A

(PDIP, CERDIP)

TOP VIEW

CSYNC

PCLK

AEN1

RDY1

READY

RDY2

AEN2

CLK

GND

ASYNC

EFI

F/C

OSC

RES

RESET

RDY1

READY

RDY2

AEN2

82C84A (PLCC, CLCC)

TOP VIEW

18 X2

ASYNC

EFI

F/C

GND

RESET

RES

OSC

FN2974 Rev 4.00

Sep 9, 2015

CLK

Page 1 of 13

82C84A

Pin Description

SYMBOL

AEN1,

AEN2

NUMBER

3, 7

TYPE

DESCRIPTION

ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready

Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are

useful in system configurations which permit the processor to access two Multi-Master System Busses.

In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW).

BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device

located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1

while RDY2 is qualified by AEN2.

READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of

the READY logic. When ASYNC is low, two stages of READY synchronization are provided. When

ASYNC is left open or HIGH, a single stage of READY synchronization is provided.

READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is

cleared after the guaranteed hold time to the processor has been met.

CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times

the desired processor clock frequency, (Note 1).

FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits the

processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is generated for the

EFI input, (Note 1).

EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input frequency

appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK

output.

PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which directly

connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crystal or EFI

input frequency and a 1/3 duty cycle.

PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK

and has a 50% duty cycle.

OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to

that of the crystal.

RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A provides a

Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper

duration.

RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing

characteristics are determined by RES.

CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be

synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset.

When CSYNC goes LOW the internal counters are allowed to resume counting. CSYNC needs to be

externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to

ground.

Ground

: The +5V power supply pin. A 0.1F capacitor between V

and GND is recommended for

decoupling.

RDY1,

RDY2

ASYNC

4, 6

READY

X1, X2

F/C

17, 16

EFI

CLK

PCLK

OSC

RES

RESET

CSYNC

GND

NOTE:

1. If the crystal inputs are not used X1 must be tied to V

or GND and X2 should be left open.

FN2974 Rev 4.00

Sep 9, 2015

Page 4 of 13

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