CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
V
DD
= V
AA
+ = V
REF
+ = 3.3V, V
SS
= V
AA
- = V
REF
- = GND, CLK = 500kHz,
Unless Otherwise Specified
25
o
C
-
40
o
C TO 85
o
C
MAX
MIN
MAX
UNITS
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL (End Point)
Differential Linearity Error, DNL
Gain Error, FSE (Adjustable to Zero)
Offset Error, V
OS
(Adjustable to Zero)
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
Total Harmonic Distortion, THD
Spurious Free Dynamic Range, SFDR
ANALOG INPUT
Input Current, Dynamic
Input Current, Static
Input Bandwidth -3dB
Reference Input Current
Input Series Resistance, R
S
Input Capacitance, C
SAMPLE
Input Capacitance, C
HOLD
DIGITAL INPUTS
OEL, OEM, STRT
High-Level Input Voltage, V
IH
Low-Level Input Voltage, V
IL
TEST CONDITIONS
MIN
TYP
12
-
-
-
-
-
-
-
-
-
-
±2.5
±2.0
±2.0
±2.5
12
-
-
-
-
-
±2.5
±2.0
±2.0
±2.5
Bits
LSB
LSB
LSB
LSB
f
S
= 500kHz, f
IN
= 1kHz
-
63.9
-
-
-
dB
f
S
= 500kHz, f
IN
= 1kHz
-
65.1
-
-
-
dB
f
S
= 750kHz, f
IN
= 1kHz
f
S
= 500kHz, f
IN
= 1kHz
-
-
-70.8
71.8
-
-
-
-
-
-
dBc
dB
At V
IN
= V
REF
+, 0V
Conversion Stopped
-
-
-
-
±50
±0.4
1
160
420
380
20
±100
±10
-
-
-
-
-
-
-
-
-
-
-
-
±100
±10
-
-
-
-
-
µA
µA
MHz
µA
W
pF
pF
In Series with Input
C
SAMPLE
During Sample State
During Hold State
-
-
-
2.4
-
-
-
-
0.8
2.4
-
-
0.8
V
V
3
HI5813
Electrical Specifications
V
DD
= V
AA
+ = V
REF
+ = 3.3V, V
SS
= V
AA
- = V
REF
- = GND, CLK = 500kHz,
Unless Otherwise Specified
(Continued)
25
o
C
PARAMETER
Input Leakage Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
OH
Low-Level Output Voltage, V
OL
Three-State Leakage, I
OZ
Output Capacitance, C
OUT
TIMING
Conversion Time (t
CONV
+ t
ACQ
)
(Includes Acquisition Time)
Clock Frequency
Clock Pulse Width, t
LOW
, t
HIGH
Aperture Delay, t
D
APR
Clock to Data Ready Delay, t
D1
DRDY
Clock to Data Ready Delay, t
D2
DRDY
Start Removal Time, t
R
STRT
Start Setup Time, t
SU
STRT
Start Pulse Width, t
W
STRT
Start to Data Ready Delay, t
D3
DRDY
Output Enable Delay, t
EN
Output Disabled Delay, t
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
DD
+ I
AA
NOTE:
2. Parameter guaranteed by design or characterization, not production tested.
//This is an example of debounce in the book module key_debounce_3 (clk_10m, rst_n, key_in, key_out); input clk_10m,rst_n,key_in; output key_out; //------------- -------------------------- reg key_rst...
[i=s]This post was last edited by 时光1111 on 2019-10-31 13:46[/i]When answering, please comment promptly
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