Changes to Ordering Guide .......................................................... 15
8/2006—Rev. 0 to Rev. A
Changes to Format ............................................................. Universal
Changes to Features and Figure 1................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Figure 19 ........................................................................ 9
Changes to Figure 25 ...................................................................... 10
Changes to Modulation Current Section and Figure 29 ........... 11
Changes to Typical Application Circuit Section......................... 13
Changes to Ordering Guide .......................................................... 15
3/2005—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
SPECIFICATIONS
ADN2525
VCC = VCC
MIN
to VCC
MAX
, T
A
= −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at
25°C, IMOD = 40 mA.
Table 1.
Parameter
BIAS CURRENT (IBIAS)
Bias Current Range
Bias Current while ALS Asserted
Compliance Voltage
1
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
Modulation Current While ALS Asserted
Rise Time (20% to 80%)
2, 3
Fall Time (20% to 80%)
2, 3
Random Jitter
2, 3
Deterministic Jitter
3, 4
Pulse-Width Distortion
2, 3
Differential |S22|
Compliance Voltage
1
DATA INPUTS (DATAP, DATAN)
Input Data Rate
Differential Input Swing
Differential |S11|
Input Termination Resistance
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
BSET Input Resistance
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
MSET Input Resistance
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
Accuracy of IBIAS to IBMON Ratio
Min
10
0.6
0.6
10
24
24
0.4
7.2
2
−10
−14
VCC − 1.1
Typ
Max
100
100
VCC – 1.2
VCC – 0.8
80
0.5
32.5
32.5
0.9
12
5
Unit
mA
µA
V
V
mA diff
mA diff
ps
ps
ps rms
ps p-p
ps
dB
dB
V
Gbps
V p-p diff
dB
Ω
mA/V
Ω
mA/V
Ω
µA/mA
%
%
%
%
V
V
µA
µA
µs
µs
See Figure 29
Test Conditions/Comments
ALS = high
IBIAS = 100 mA
IBIAS = 10 mA
R
LOAD
= 5 Ω to 50 Ω differential
ALS = high
Includes pulse-width distortion
PWD = ABS(T
HIGH
− T
LOW
)/2
5 GHz < f < 10 GHz, Z
0
= 50 Ω differential
f < 5 GHz, Z
0
= 50 Ω differential
VCC + 1.1
10.7
1.6
−16.8
100
100
1000
88
1000
10
115
120
1200
110
1200
0.4
85
75
800
70
800
NRZ
Differential ac-coupled
f < 10 GHz, Z
0
= 100 Ω differential
Differential
−5.0
−4.0
−2.5
−2
2.4
−20
0
+5.0
+4.0
+2.5
+2
10 mA ≤ IBIAS < 20 mA, R
IBMON
= 1 kΩ
20 mA ≤ IBIAS < 40 mA, R
IBMON
= 1 kΩ
40 mA ≤ IBIAS < 70 mA, R
IBMON
= 1 kΩ
70 mA ≤ IBIAS < 100 mA, R
IBMON
= 1 kΩ
AUTOMATIC LASER SHUTDOWN (ALS)
V
IH
V
IL
I
IL
I
IH
ALS Assert Time
ALS Negate Time
POWER SUPPLY
V
CC
I
CC 5
I
SUPPLY 6
0.8
+20
200
2
10
Rising edge of ALS to fall of IBIAS and
IMOD below 10% of nominal; see Figure 2
Falling edge of ALS to rise of IBIAS and
IMOD above 90% of nominal; see Figure 2
3.07
3.3
39
157
3.53
45
176
V
mA
mA
V
BSET
= V
MSET
= 0 V
V
BSET
= V
MSET
= 0 V; I
SUPPLY
= I
CC
+ IMODP + IMODN
See notes on next page.
Rev. B | Page 3 of 16
ADN2525
1
2
Data Sheet
Refers to the voltage between the pin for which the compliance voltage is specified and GND.
The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
3
Measured using the high speed characterization circuit shown in Figure 3.
4
The pattern used is K28.5 (00111110101100000101) at a 10.7 Gbps rate.
5
Only includes current in the ADN2525 VCC pins.
6
Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
THERMAL SPECIFICATIONS
Table 2.
Parameter
θ
J-PAD
θ
J-TOP
IC Junction Temperature
Min
2.6
65
Typ
5.8
72.2
Max
10.7
79.4
125
Unit
°C/W
°C/W
°C
Conditions/Comments
Thermal resistance from junction to bottom of exposed pad
Thermal resistance from junction to top of package
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