HSP43124
Serial I/O Filter
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DATASHEET
FN3555
Rev 7.00
April 18, 2007
The Serial I/O Filter is a high performance filter engine that is
ideal for off loading the burden of filter processing from a DSP
microprocessor. It supports a variety of multistage filter
configurations based on a user programmable filter and fixed
coefficient halfband filters. These configurations include a
programmable FIR filter of up to 256 taps, a cascade of from
one to five halfband filters, or a cascade of halfband filters
followed by a programmable FIR. The half band filters each
decimate by a factor of two, and the FIR filter decimates from
one to eight. When all six filters are selected, a maximum
decimation of 256 is provided.
For digital tuning applications, a separate multiplier is provided
which allows the incoming data stream to be multiplied, or
mixed, by a user supplied mix factor. A two pin interface is
provided for serially loading the mix factor from an external
source or selecting the mix factor from an on-board ROM. The
on-board ROM contains samples of a sinusoid capable of
spectrally shifting the input data by one quarter of the sample
rate, F
S
/4. This allows the chip to function as a digital down
converter when the filter stages are configured as a low-pass
filter.
The serial interface for
3-
input and output data is compatible
with the serial ports of common DSP microprocessors.
Coefficients and configuration data are loaded over a
bidirectional eight bit interface.
Features
• 45MHz Clock Rate
• 256 Tap Programmable FIR Filter
• 24-Bit Data, 32-Bit Coefficients
• Cascade of up to 5 Half Band Filters
• Decimation from 1 to 256
• Two Pin Interface for Down Conversion by F
S
/4
• Multiplier for Mixing or Scaling Input with an External
Source
• Serial I/O Compatible with Most DSP Microprocessors
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Low Cost FIR Filter
• Filter Co-Processor
• Digital Tuner
Ordering Information
PART NUMBER
HSP43124SC-45
PART MARKING
HSP43124SC-45
TEMP.
RANGE (°C)
0 to +70
0 to +70
PACKAGE
28 Ld SOIC (300 mil)
28 Ld SOIC (300 mil, Pb-free)
PKG. NO.
M28.3
M28.3
HSP43124SC-45Z (Note) HSP43124SC-45Z
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
INPUT
FORMATTER
OUTPUT
FORMATTER
DIN
SCLK
SYNCIN
MXIN
SYNCMX
HALF
BAND
FILTER
#1
HALF
BAND
FILTER
#2
HALF
BAND
FILTER
#5
PROGRAMMABLE
FIR
FILTER
DOUT
SYNCOUT
CLKOUT
CONTROL
INTERFACE
A0-2
C0-7
WR
RD
FN3555 Rev 7.00
April 18, 2007
FSYNC
FCLK
Page 1 of 18
HSP43124
Pinout
HSP43124
(28 LD PDIP, SOIC)
TOP VIEW
SCLK 1
SYNCIN 2
GND 3
MXIN 4
SYNCMX 5
FSYNC 6
V
CC
7
FCLK 8
WR 9
RD 10
A0 11
A1 12
A2 13
V
CC
14
28 DIN
27 DOUT
26 SYNCOUT
25 CLKOUT
24 V
CC
23 C7
22 C6
21 C5
20 C4
19 GND
18 C3
17 C2
16 C1
15 C0
FN3555 Rev 7.00
April 18, 2007
Page 2 of 18
HSP43124
Pin Description
NAME
V
CC
GND
DIN
TYPE
-
-
I
+5V Power Supply
Ground
Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A “HIGH” on this input
represents a “1”, and a low on this input represents “0”. The word format and operation of serial interface are con-
tained in the Data Input Section.
Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples
SYNCIN “HIGH” one SCLK before the first bit of the new word.
NOTE: SYNCIN should not maintain a “HIGH”
state for longer than one SCLK cycle.
Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the part. The following signals are
synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX.
Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A “HIGH” on
this input represents a “1”, and a low on this input represents “0”. Also used to specify the Weaver Modulator ROM
output as a part of the two pin F
S/
4 down conversion interface. Details on word format and operation are contained
in the Mix Factor Section.
Mix Factor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples
SYNCMX “HIGH” one SCLK before the first bit of the new mix factor.
NOTE: SYNCMX should only pulse “HIGH”
for one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin F
S
/4 down
conversion interface.
Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate require-
ments on FCLK for particular filter configurations is discussed in the Filter Compute Engine Section. This clock
may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock.
Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the
data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is
currently being input, the current sum of products and the input data are “canceled” and the DIN pin is ignored until
the next SYNCIN cycle occurs.
Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by
the address on A0-2. The WR signal is asynchronous to all other clocks.
NOTE: WR should not be low when
RD is low.
Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places
the contents of that memory location on C0-7. When RD returns “HIGH” the C0-7 bus functions as an input bus.
The RD pin is asynchronous to all other clocks.
NOTE: RD should not be low when WR is low.
Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address
map for the control registers.
Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM.
Output Clock. Programmable bit clock for serial output.
NOTE: Assertion of FSYNC initializes CLKOUT to a
high state.
Output Data Sync. SYNYOUT is asserted HIGH for one CLKOUT cycle before the first bit of a new output sample
is available on DOUT.
Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter
section for additional details.)
DESCRIPTION
SYNCIN
I
SCLK
MXIN
I
I
SYNCMX
I
FCLK
I
FSYNC
I
WR
I
RD
I
A0-2
C0-7
CLKOUT
SYNCOUT
DOUT
I
I/O
O
O
O
FN3555 Rev 7.00
April 18, 2007
Page 3 of 18
HSP43124
INPUT FORMATTER
VARIABLE LENGTH
SHIFT REGISTER
(8-24-BITS)
# BITS
†
MSB F/2
†
FORMAT
†
SYNCIN
FILTER COMPUTE ENGINE
OUTPUT
FORMATTER
MULTIPLY/
ACCUMULATOR
DIN
SYNCIN
57
INPUT
HOLDING
REG
MIX FACTOR
HOLDING
REG
SYNCMX
MSB F/L
†
FCLK
†
CLKOUT
# BITS
†
SYNCOUT
ROUND/
SATURATE
CLKOUT
DOUT
SERIAL
MULTIPLIER
M
U
48 X
ROUND/
SATURATE
24
REGISTER
FILE
+
25
+
R
E
G
MUX
SYNCMX
MIX
MXIN
SEL
†
WEAVER
MODULATOR
ROM
CONTROL
†
PARAMETERS
†
32
FILT EN
†
# HBs
†
MUX
ROUND
†
DECIMATION FORMAT
†
RATE
†
GAIN COR
†
FIR SYM
†
COEFFICIENT
RAM
RD EN
†
FILTER LENGTH
†
RAM ACCESS
†
CONTROL
HALFBAND
COEFFICIENT
ROM
MXIN
VARIABLE LENGTH
SHIFT REGISTER
(8 TO 24 BITS)
# BITS
†
FORMAT
†
A0-2
C0-7
WR
RD
FSYNC
FCLK
SCLK
†Indicates
configuration control word data parameter.
FIGURE 1. SERIAL FILTER BLOCK DIAGRAM
Functional Descriptions
The HSP43124 is a high performance digital filter designed to
process a serial input data stream. A second serial interface is
provided for mix factor inputs, which are multiplied by the input
samples as shown in Figure 1. The multiplier result is passed to
the Filter Compute Engine for processing.
The Filter Compute Engine centers around a single
multiply/accumulator (MAC). The MAC performs the sum-of-
products required by a particular filter configuration. The
processing rate of the MAC is determined by the filter clock,
FCLK. Increasing FCLK relative to the input sample rate
increases the length of filter that can be realized.
The filtered results are passed to the Output Formatter where
they are rounded or truncated to a user defined bit width. The
Output Formatter then generates the timing and synchronization
signals required to serially transmit the data to an external
device.
data, C0-7, be stable and valid on the falling edge of the WR, as
shown in Figure 2.
NOTE: WR should not be active low when
RD is active low.
Data is read from the configuration control registers on the
falling edge of the RD input. The contents of a particular register
are accessed by setting up an address, A0-2, to the falling edge
of RD as shown in Figure 2. The data is output on C0-7. The
data on C0-7 remains valid until RD returns HIGH, at which point
the C0-7 bus is Three-Stated and functions as an input. For
proper operation, the address on A0-2 must be held until RD
returns “high” as shown in Figure 2.
NOTE: RD should not be
active low when WR is active low.
WRITE TIMING
WR
A0-2
C0-7
READ TIMING
RD
A0-2
C0-7
Filter Configuration
The HSP43124 is configured for operation by loading a set of
eight control registers. These registers are written through a
bidirectional interface which is also used for reading the control
registers. The interface consists of an 8-bit data bus, C0-7, a 3-
bit address bus, A0-2, and read/write lines, RD and WR. The
address map for the control registers is shown in Table 1.
Data is written to the configuration control registers on the falling
edge of the WR input. This requires that the address, A0-2, and
FIGURE 2. READ/WRITE TIMING
FN3555 Rev 7.00
April 18, 2007
Page 4 of 18
HSP43124
TABLE 1. CONFIGURATION CONTROL REGISTER FUNCTIONAL DESCRIPTION
ADDRESS
000
REGISTER DESCRIPTION
Filter Configuration
BIT
POSITIONS
2-0
3
4
BIT FUNCTION
Specifies the number of halfbands to use. Number ranges from 0 to 5. Other
values are invalid.
Filter Enable bit. 1 = Enable. 0 = Minimum filter bypass (either the FIR or
HBF must be enabled to get an output).
Coefficient read enable. When set to 1, enables reading and disables writing
of coefficient RAM.
NOTE: This bit must be set to 0 prior to writing the
Coefficient RAM.
FIR Decimation Rate. Range is 1-8 (8 = 000).
Number of Taps in the Programmable FIR Filter. For even or odd symmetric
filters, values range from 4- 256, 1 to 3 are invalid, and 0000000 = 256. For
asymmetric filters, the value loaded in this register must be two times the ac-
tual number of coefficients.
Coefficient RAM is loaded by multiple writes to this address. (See Writing
Coefficients section for additional details.)
Number of bits in input data word, from 8 (01000) to 24 (11000). Values out-
side the range of 8 - 24 are invalid.
Number System. 0 = Two’s Complement, 1 = Offset Binary.
Serial Format. 1 = MSB First, 0 = LSB First.
Unused
Number of FCLKS per CLKOUT. Range 1 to 32. (00000 = 32 FCLKS)
1 = MSB First, 0 = LSB First.
Unused
Number of bits in output data word, from 8 to 32. A value of 32 is represented
by 00000, and values from 1 to 7 are invalid.
Round Select. 1 = Round to Selected Number of Bits, 0 = Truncate.
Number System. 0 = Two’s Complement, 1 = Offset Binary.
Gain Correction. 1 = Apply scale factor of 2 to data. 0 = No Scaling.
00 = Even Symmetric FIR Coefficients
01 = Non-Symmetric Coefficients
10 = Odd Symmetric FIR
Reserved: Must be 0.
Number of bits in mix factor, from 8 (01000) to 24 (11000). Values outside
the range of 8 - 24 are invalid.
Serial Format. 1 = MSB First, 0 = LSB First.
Mix Factor Select. 1 = Serial Input, 0 = Weaver modulator look-up-table.
Unused
7-5
001
Programmable FIR Filter Length
7-0
010
011
Coefficient RAM Access
Input Format
7-0
4-0
5
6
7
100
Output Timing
4-0
5
6-7
101
Output Format
4-0
5
6
7
110
Filter Symmetry
1-0
7-2
111
Mix Factor Format
4-0
5
6
7
Writing Coefficients
The HSP43124 provides a register bank to store filter
coefficients for configurations which use the programmable
filter. The register bank consists of 128 thirty-two-bit registers.
Each register is loaded by 4 one byte writes to the bidirectional
interface used for loading the configuration registers. The
coefficients are loaded in order from least significant byte
(LSB) to most significant byte (MSB).
The coefficient registers are loaded by first setting the
coefficient read enable bit to “0” (bit 4 of the Filter Configuration
Register). Next, coefficients are loaded by setting the A2-0
address to 010 (binary) and writing one byte at a time as
shown in Figure 3. The down loaded bytes are stored in a
holding register until the 4th write cycle. On completion of the
fourth write cycle, the contents of the holding register are
loaded into the Coefficient RAM, and the write pointer is
incremented to the next register. If the user attempts to write
more than 128 coefficients, the pointer halts at the 128th
FN3555 Rev 7.00
April 18, 2007
Page 5 of 18
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