HSP43124SC-45Z datasheet, PDF - EEWORLD Datasheet

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HSP43124SC-45Z: Description1-BIT, DSP-DIGITAL FILTER, PDSO28; Categorysemiconductor The embedded processor and controller; File Size464KB，18 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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1-BIT, DSP-DIGITAL FILTER, PDSO28

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HSP43124

Serial I/O Filter

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DATASHEET

FN3555

Rev 7.00

April 18, 2007

The Serial I/O Filter is a high performance filter engine that is

ideal for off loading the burden of filter processing from a DSP

microprocessor. It supports a variety of multistage filter

configurations based on a user programmable filter and fixed

coefficient halfband filters. These configurations include a

programmable FIR filter of up to 256 taps, a cascade of from

one to five halfband filters, or a cascade of halfband filters

followed by a programmable FIR. The half band filters each

decimate by a factor of two, and the FIR filter decimates from

one to eight. When all six filters are selected, a maximum

decimation of 256 is provided.

For digital tuning applications, a separate multiplier is provided

which allows the incoming data stream to be multiplied, or

mixed, by a user supplied mix factor. A two pin interface is

provided for serially loading the mix factor from an external

source or selecting the mix factor from an on-board ROM. The

on-board ROM contains samples of a sinusoid capable of

spectrally shifting the input data by one quarter of the sample

rate, F

/4. This allows the chip to function as a digital down

converter when the filter stages are configured as a low-pass

filter.

The serial interface for

input and output data is compatible

with the serial ports of common DSP microprocessors.

Coefficients and configuration data are loaded over a

bidirectional eight bit interface.

Features

• 45MHz Clock Rate

• 256 Tap Programmable FIR Filter

• 24-Bit Data, 32-Bit Coefficients

• Cascade of up to 5 Half Band Filters

• Decimation from 1 to 256

• Two Pin Interface for Down Conversion by F

• Multiplier for Mixing or Scaling Input with an External

Source

• Serial I/O Compatible with Most DSP Microprocessors

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Low Cost FIR Filter

• Filter Co-Processor

• Digital Tuner

Ordering Information

PART NUMBER

HSP43124SC-45

PART MARKING

HSP43124SC-45

TEMP.

RANGE (°C)

0 to +70

PACKAGE

28 Ld SOIC (300 mil)

28 Ld SOIC (300 mil, Pb-free)

PKG. NO.

M28.3

HSP43124SC-45Z (Note) HSP43124SC-45Z

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Block Diagram

INPUT

FORMATTER

OUTPUT

FORMATTER

DIN

SCLK

SYNCIN

MXIN

SYNCMX

HALF

BAND

FILTER

HALF

BAND

FILTER

HALF

BAND

FILTER

PROGRAMMABLE

FIR

FILTER

DOUT

SYNCOUT

CLKOUT

CONTROL

INTERFACE

A0-2

C0-7

FN3555 Rev 7.00

April 18, 2007

FSYNC

FCLK

Page 1 of 18

HSP43124

Pin Description

NAME

GND

DIN

TYPE

+5V Power Supply

Ground

Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A “HIGH” on this input

represents a “1”, and a low on this input represents “0”. The word format and operation of serial interface are con-

tained in the Data Input Section.

Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples

SYNCIN “HIGH” one SCLK before the first bit of the new word.

NOTE: SYNCIN should not maintain a “HIGH”

state for longer than one SCLK cycle.

Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the part. The following signals are

synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX.

Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A “HIGH” on

this input represents a “1”, and a low on this input represents “0”. Also used to specify the Weaver Modulator ROM

output as a part of the two pin F

4 down conversion interface. Details on word format and operation are contained

in the Mix Factor Section.

Mix Factor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples

SYNCMX “HIGH” one SCLK before the first bit of the new mix factor.

NOTE: SYNCMX should only pulse “HIGH”

for one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin F

/4 down

conversion interface.

Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate require-

ments on FCLK for particular filter configurations is discussed in the Filter Compute Engine Section. This clock

may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock.

Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the

data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is

currently being input, the current sum of products and the input data are “canceled” and the DIN pin is ignored until

the next SYNCIN cycle occurs.

Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by

the address on A0-2. The WR signal is asynchronous to all other clocks.

NOTE: WR should not be low when

RD is low.

Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places

the contents of that memory location on C0-7. When RD returns “HIGH” the C0-7 bus functions as an input bus.

The RD pin is asynchronous to all other clocks.

NOTE: RD should not be low when WR is low.

Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address

map for the control registers.

Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM.

Output Clock. Programmable bit clock for serial output.

NOTE: Assertion of FSYNC initializes CLKOUT to a

high state.

Output Data Sync. SYNYOUT is asserted HIGH for one CLKOUT cycle before the first bit of a new output sample

is available on DOUT.

Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter

section for additional details.)

DESCRIPTION

SYNCIN

SCLK

MXIN

SYNCMX

FCLK

FSYNC

A0-2

C0-7

CLKOUT

SYNCOUT

DOUT

I/O

FN3555 Rev 7.00

April 18, 2007

Page 3 of 18

HSP43124SC-45Z Related Products

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Description	1-BIT, DSP-DIGITAL FILTER, PDSO28	1-BIT, DSP-DIGITAL FILTER, PDSO28	1-BIT, DSP-DIGITAL FILTER, PDSO28

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