Features
•
1.65V - 1.95V Read/Write
•
High Performance
– Random Access Time – 70 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
Sector Erase Architecture
– Sixteen 4K Word Sectors with Individual Write Lockout
– Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one
Planes not Being Programmed/Erased
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
CBGA and TSOP Packages
Seventeen 128-bit Protection Registers (2,176 Bits)
Common Flash Interface (CFI)
•
•
•
•
•
•
•
•
•
•
128-megabit
(8M x 16)
Burst/Page
Mode 1.8-volt
Flash Memory
AT49SN12804
AT49SV12804
Description
The AT49SN/SV12804 is a 1.8-volt 128-megabit Flash memory. The memory is
divided into multiple sectors and planes for erase operations. The AT49SN/SV12804
is organized as 8,388,608 x 16 bits. The device can be read or reprogrammed off a
single 1.8V power supply, making it ideally suited for In-System programming. The
device can be configured to operate in the asynchronous/page read (default mode) or
burst read mode (not available for the AT49SV12804). The burst read mode is used to
achieve a faster data rate than is possible in the asynchronous/page read mode. If the
AVD and the CLK signals are both tied to GND and the burst configuration register is
configured to perform asynchronous reads, the device will behave like a standard
asynchronous Flash memory. In the page mode, the AVD signal can be tied to GND or
can be pulsed low to latch the page address. In both cases the CLK can be tied to
GND.
The AT49SN/SV12804 is divided into thirty-two memory planes. A read operation can
occur in any of the thirty-one planes which is not being programmed or erased. This
concurrent operation allows improved system performance by not requiring the sys-
tem to wait for a program or erase operation to complete before a read is performed.
To further increase the flexibility of the device, it contains an Erase Suspend and Pro-
gram Suspend feature. This feature will put the erase or program on hold for any
amount of time and let the user read data from or program data to any of the remain-
ing sectors. There is no reason to suspend the erase or program operation if the data
to be read is in another memory plane.
The VPP pin provides data protection and faster programming and erase times. When
the V
PP
input is below 0.4V, the program and erase functions are inhibited. When V
PP
is at 0.9V or above, normal program and erase operations can be performed. With V
PP
at 12.0V, the program (Dual-word Program command) and erase operations are
accelerated.
Preliminary
Rev. 3314A–FLASH–4/04
1
AT49SN/SV12804: Pin Configurations
Pin Name
I/O0 - I/O15
A0 - A22
CE
OE
WE
AVD
(1)
CLK
(1)
RESET
WP
(1)
VPP
WAIT
(1)
VCCQ
Note:
Pin Function
Data Inputs/Outputs
Addresses
Chip Enable
Output Enable
Write Enable
Address Latch Enable
Clock
Reset
Write Protect
Write Protection and Power Supply for Accelerated Program Operations
WAIT
Output Power Supply
1. These signals are not available for use with the AT49SV12804. The AT49SV12804 can only be used in the asynchro-
nous/page mode.
AT49SN12804: CBGA – Top View
1
2
3
4
5
6
7
8
AT49SV12804: TSOP – Top View
Type 1
A21
NC
A20
A19
A18
A17
A16
A15
VCC
A14
A13
A12
A11
CE
VPP
RST
A10
A9
A8
A7
VSS
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
WE
OE
NC
I/O15
I/O7
I/O14
I/O6
VSS
I/O13
I/O5
I/O12
I/O4
VCCQ
VSS
I/O11
I/O3
I/O10
I/O2
VCC
I/O9
I/O1
I/O8
I/O0
NC
NC
A22
NC
A
B
C
D
E
F
G
A11
A12
A8 VSS VCC VPP A18
A9
A20 CLK RESET A17
A6
A5
A7
A4
A3
A2
A1
A0
A13 A10 A21 AVD WE A19
A15 A14 WAIT A16 I/O12 WP A22
VCCQ I/O15 I/O6 I/O4 I/O2 I/O1 CE
VSS I/O14 I/013 I/O11 I/O10 I/O9 I/O0 OE
I/O7 VSS I/O5 VCC I/O3 VCCQ I/O8 VSS
2
AT49SN/SV12804 [Preliminary]
3314A–FLASH–4/04
AT49SN/SV12804 [Preliminary]
Device
Operation
COMMAND SEQUENCES:
When the device is first powered on, it will be in the read mode.
Command sequences are used to place the device in other operating modes such as program
and erase. The command sequences are written by applying a low pulse on the WE input with
CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE
high. Prior to the low-going pulse on the CE or WE signal, the address input may be latched by
a low-to-high transition on the AVD signal. If the AVD is not pulsed low, the address will be
latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the
WE or the CE pulse, whichever occurs first. The addresses used in the command sequences
are not affected by entering the command sequences.
BURST CONFIGURATION COMMAND:
The Program Burst Configuration Register command
is used to program the burst configuration register. The burst configuration register determines
several parameters that control the read operation of the device. Bit B15 determines whether
synchronous burst reads are enabled or asynchronous reads are enabled. Since the page
read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to
enable the page read feature. Bit B14 determines whether a four-word page or an eight-word
page will be used. The rest of the bits in the burst configuration register are used only for the
burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency
for the burst mode. The latency can be set to two, three, four, five or six cycles. The clock
latency versus input clock frequency table is shown on page 20. The “Burst Read Waveform”
as shown on page 31 illustrates a clock latency of four; the data is output from the device four
clock cycles after the first valid clock edge following the high-to-low AVD edge. The B10 bit of
the configuration register determines the polarity of the WAIT signal. The B9 bit of the burst
configuration register determines the number of clocks that data will be held valid (see Figure
4). The Hold Data for 2 Clock Cycles Read Waveform is shown on page 31. The clock latency
is not affected by the value of the B9 bit. The B8 bit of the burst configuration register deter-
mines when the WAIT signal will be asserted. When synchronous burst reads are enabled, a
linear burst sequence is selected by setting bit B7. Bit B6 selects whether the burst starts and
the data output will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of
the burst configuration register determine whether a continuous or fixed-length burst will be
used and also determine whether a four-, eight- or sixteen-word length will be used in the
fixed-length mode. When a four-, eight- or sixteen-word burst length is selected, Bit B3 can be
used to select whether burst accesses wrap within the burst length boundary or whether they
cross word length boundaries to perform linear accesses (see Table 5). All other bits in the
burst configuration register should be programmed as shown on page 20. The default state
(after power-up or reset) of the burst configuration register is also shown on page 20.
ASYNCHRONOUS READ:
There are two types of asynchronous reads – AVD pulsed and
standard asynchronous reads. The AVD pulsed read operation of the device is controlled by
CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE
is high. This dual-line control gives designers flexibility in preventing bus contention. The data
at the address location defined by A0 - A22 and captured by the AVD signal will be read when
CE and OE are low. The address location passes into the device when CE and AVD are low;
the address is latched on the low-to-high transition of AVD. Low input levels on the OE and CE
pins allow the data to be driven out of the device. The access time is measured from stable
address, falling edge of AVD or falling edge of CE, whichever occurs last. During the AVD
pulsed read, the CLK signal may be static high or static low. For standard asynchronous
reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are
shown on page 28.
PAGE READ:
The page read operation of the device is controlled by CE, OE, and AVD inputs.
The CLK input is ignored during a page read operation and should be tied to GND. The page
size can be four words (default value) or eight words depending on what value bit B14 of the
burst configuration register is programmed to. During a page read, the AVD signal can transi-
tion low and then transition high, transition low and remain low, or can be tied to GND. If a high
to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1, the
3
3314A–FLASH–4/04
page address is latched by the low-to-high transition of the AVD signal. However, if the AVD
signal remains low after the high-to-low transition or if the AVD signal is tied to GND, as shown
in Page Read Cycle Waveform 2, then the page address (determined by A22 - A3 for an eight
word page and A22 - A2 for a four-word page) cannot change during a page read operation.
The first word access of the page read is the same as the asynchronous read. The first word is
read at an asynchronous speed of 90 ns. Once the first word is read, toggling A0 and A1 (four-
word page mode) or toggling A0, A1, and A2 (eight word page mode) will result in subsequent
reads within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both
tied to GND, the device will behave like a standard asynchronous Flash memory. The page
read diagrams are shown on page 22.
SYNCHRONOUS READS:
Synchronous reads (not available on the AT49SV12804) are used
to achieve a faster data rate that is possible in the asynchronous/page read mode. The device
can be configured for continuous or fixed-length burst access. The burst read operation of the
device is controlled by CE, OE, CLK and AVD inputs. The initial read location is determined as
for the AVD pulsed asynchronous read operation; it can be any memory location in the device.
In the burst access, the address is latched on the rising edge of the first clock pulse when AVD
is low or the rising edge of the AVD signal, whichever occurs first. The CLK input signal con-
trols the flow of data from the device for a burst operation. After the clock latency cycles, the
data at the next burst address location is read for each following clock cycle.
Figure 1.
Word Boundary
Word D0 - D3
D0 D1
D2
Word D4 - D7
D5
D6 D7
Word D8 - D11
Word D12 - D15
D3 D4
D8 D9 D10 D11 D12 D13 D14 D15
16-word Boundary
CONTINUOUS BURST READ:
During a continuous burst read, any number of addresses can
be read from the memory. When operating in the linear burst read mode (B7 = 1) with
the burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst
sequence crosses the first 16-word boundary in the memory (see Figure 1). If the starting
address is D0 - D12, there is no delay. If the starting address is D13 - D15, an output delay
equal to the initial clock latency is incurred. The delay takes place only once, and only if the
burst sequence crosses a 16-word boundary. To indicate that the device is not ready to con-
tinue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the clock cycles
in which new data is not being presented. Once the WAIT pin is driven high (B10 and B8 = 0),
the current data will be valid. The WAIT signal will be tri-stated when the CE or OE signal is
high.
In the “Burst Read Waveform” as shown on page 31, the valid address is latched at point A.
For the specified clock latency of three, data D13 is valid within 13 ns of clock edge B. The
low-to-high transition of the clock at point C results in D14 being read. The transition of the
clock at point D results in a burst read of D15. The clock transition at point E does not cause
new data to appear on the output lines because the WAIT signal goes low (B10 and B8 = 0)
after the clock transition, which signifies that the first boundary in the memory has been
crossed and that new data is not available. After a clock latency of three, the clock transition at
point F does cause a burst read of data D16 because the WAIT signal goes high (B10 and B8
= 0) after the clock transition indicating that new data is available. Additional clock transitions,
like at point G, will continue to result in burst reads.
4
AT49SN/SV12804 [Preliminary]
3314A–FLASH–4/04
AT49SN/SV12804 [Preliminary]
FIXED-LENGTH BURST READS:
During a fixed-length burst mode read, four, eight or six-
teen words of data may be burst from the device, depending upon the configuration. The
device supports a linear burst mode. The burst sequence is shown on page 21. When operat-
ing in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may
incur an output delay when the burst sequence crosses the first 16-word boundary in the
memory. If the starting is D0 - D12, there is no delay. If the starting address is D13 - D15, an
output delay equal to the initial clock latency is incurred. The delay takes place only once, and
only if the burst sequence crosses a 16-word boundary. To indicate that the device is not
ready to continue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the
clock cycles in which new data is not being presented. Once the WAIT pin is driven high (B10
and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated when the CE or
OE signal is high.
The “Four-word Burst Read Waveform” on page 32 illustrates a fixed-length burst cycle. The
valid address is latched at point A. For the specified clock latency of four, data D0 is valid
within 13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1
being read. Similarly, D2 and D3 are output following the next two clock cycles. Returning CE
high ends the read cycle. There is no output delay in the burst access wrap mode (B3 = 0).
BURST SUSPEND:
The Burst Suspend feature allows the system to temporarily suspend a
synchronous burst operation if the system needs to use the Flash address and data bus for
other purposes. Burst accesses can be suspended during the initial latency (before data is
received) or after the device has output data. When a burst access is suspended, internal
array sensing continues and any previously latched internal data is retained.
Burst Suspend occurs when CE is asserted, the current address has been latched (either ris-
ing edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be
halted when it is at V
IH
or V
IL
. To resume the burst access, OE is reasserted and the CLK is
restarted. Subsequent CLK edges resume the burst sequence where it left off.
Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT sig-
nal reverts to a high-impedance state when OE is deasserted. See “Burst Suspend Waveform”
on page 32.
RESET:
A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET pin
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to read mode.
ERASE:
Before a word can be reprogrammed it must be erased. The erased state of the
memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase com-
mand or individual planes can be erased by using the Plane Erase command or individual
sectors can be erased by using the Sector Erase command.
5
3314A–FLASH–4/04
京公网安备 11010802033920号
EEWORLD
