74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
October 2000
Revised March 2005
74LCXZ245
Low Voltage Bidirectional Transceiver
with 5V Tolerant Inputs and Outputs
General Description
The 74LCXZ245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The device is designed for low voltage
(2.5V and 3.3V) V
CC
applications with capability of interfac-
ing to a 5V signal environment. The T/R input determines
the direction of data flow through the device. The OE input
disables both the A and B ports by placing them in a high
impedance state.
The 74LCXZ245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation. When V
CC
is between 0V
and 1.5V, the 74LCXZ245 is on the high impedance state
during power up or power down. This places the outputs in
the high impedance (Z) state preventing intermittent low
impedance loading or glitching in bus oriented applications.
Features
s
5V tolerant inputs and outputs
s
2.3V–3.6V V
CC
specifications provided
s
7.0 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
r
24 mA output drive (V
CC
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCXZ245WM
74LCXZ245SJ
74LCXZ245MSA
74LCXZ245MTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
T/R
A
0
–A
7
B
0
–B
7
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 2005 Fairchild Semiconductor Corporation
DS500362
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74LCXZ245
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
V
I
GND
V
O
GND
V
O
!
V
CC
V
mA
mA
mA
mA
mA
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
0.5 to V
CC
0.5
50
50
50
r
50
r
100
r
100
65 to
150
q
C
Recommended Operating Conditions
(Note 5)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
3-STATE
V
CC
V
CC
V
CC
T
A
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V
2.0V, V
CC
3.0V
3.0V
3.6V
2.7V - 3.0V
2.3V - 2.7V
Parameter
Operating
Min
2.7
0
0
0
Max
3.6
5.5
V
CC
5.5
Units
V
V
V
r
24
r
12
r
8
40
0
85
10
mA
q
C
ns/V
'
t/
'
V
Note 3:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4:
I
O
Absolute Maximum Rating must be observed.
Note 5:
Unused inputs or I/O pins must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
I
PU/PD
Input Leakage Current
3-STATE I/O Leakage
Power-Off Leakage Current
Power Up/ Power Down
3-STATE Output Current
Conditions
V
CC
(V)
2.3
2.7
2.7
3.6
2.3
2.7
2.7 - 3.6
T
A
40
q
C to
85
q
C
Max
Min
1.7
2.0
Units
V
0.7
0.8
V
CC
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
V
100
P
A
8 mA
12 mA
18 mA
24 mA
100
P
A
8mA
12 mA
16 mA
24 mA
2.3 - 3.6
2.3
2.7
3.0
3.0
2.3
3.6
2.3
2.7
3.0
3.0
2.3
3.6
2.3
3.6
0
0
1.5
V
V
0
d
V
I
d
5.5V
0
d
V
O
d
5.5V
V
I
V
O
V
I
V
IH
or V
IL
5.5V
to V
CC
V
CC
or GND
V
I
or V
O
r
5.0
r
5.0
10
P
A
P
A
P
A
P
A
r
5.0
3
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74LCXZ245
DC Electrical Characteristics
Symbol
I
CC
Parameter
Quiescent Supply Current
Increase in I
CC
per Input
V
I
V
IH
(Continued)
V
CC
(V)
V
CC
or GND
V
CC
0.6V
2.3
3.6
2.3
3.6
2.3
3.6
T
A
Conditions
40
q
C to
85
q
C
Max
225
Units
Min
3.6V
d
V
I
, V
O
d
5.5V (Note 6)
r
225
500
P
A
P
A
'
I
CC
Note 6:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
C
L
Min
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSHL
t
OSLH
Output to Output Skew
(Note 7)
Output Disable Time
Propagation Delay
A
n
to B
n
or B
n
to A
n
Output Enable Time
1.5
1.5
1.5
1.5
1.5
1.5
40
q
C to
85
q
C, R
L
50 pF
Max
7.0
7.0
8.5
8.5
7.5
7.5
1.0
1.0
C
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
500
:
2.7V
50 pF
Max
8.0
8.0
9.5
9.5
8.5
8.5
ns
ns
ns
ns
Units
3.3V
r
0.3V
V
CC
Note 7:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
C
L
C
L
C
L
C
L
50 pF, V
IH
30 pF, V
IH
50 pF, V
IH
30 pF, V
IH
Conditions
3.3V, V
IL
2.5V, V
IL
3.3V, V
IL
2.5V, V
IL
0V
0V
0V
0V
V
CC
(V)
3.3
2.5
3.3
2.5
T
A
25
q
C
0.8
0.6
Typical
Units
V
V
0.8
0.6
Capacitance
Symbol
C
IN
C
I/O
C
PD
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
Parameter
V
CC
V
CC
V
CC
Open, V
I
3.3V, V
I
3.3V, V
I
Conditions
0V or V
CC
0V or V
CC
0V or V
CC
, f
10 MHz
Typical
7
8
25
Units
pF
pF
pF
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4
74LCXZ245
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Test
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
,t
PHZ
Switch
Open
6V at V
CC
3.3
r
0.3V
V
CC
x 2 at V
CC
2.5
r
0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and t
rec
Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
R
= t
F
= 3ns)
Symbol
V
mi
V
mo
V
x
V
y
V
CC
3.3V
r
0.3V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
2.7V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
t
rise
and t
fall
2.5V
r
0.2V
V
CC
/2
V
CC
/2
V
OL
0.15V
V
OH
0.15V
5
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