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74LVQ125SJ

Description
Low Voltage Quad Buffer with 3-STATE Outputs
Categorylogic    logic   
File Size51KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVQ125SJ Overview

Low Voltage Quad Buffer with 3-STATE Outputs

74LVQ125SJ Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instruction5.30 MM, EIAJ TYPE2, SOP-14
Contacts14
Reach Compliance Codecompli
Is SamacsysN
Control typeENABLE LOW
seriesLVQ
JESD-30 codeR-PDSO-G14
JESD-609 codee3
length10.2 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.012 A
Humidity sensitivity level1
Number of digits1
Number of functions4
Number of ports2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTUBE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su10 ns
propagation delay (tpd)14 ns
Certification statusNot Qualified
Maximum seat height2.1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width5.3 mm
Base Number Matches1
74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs
February 1992
Revised June 2001
74LVQ125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVQ125 contains four independent non-inverting buff-
ers with 3-STATE outputs.
Features
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Guaranteed incident wave switching into 75
Ordering Code:
Order Number
74LVQ125SC
74LVQ125SJ
Package Number
M14A
M14D
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
Truth Table
Inputs
A
n
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
HIGH Impedance
X
=
Immaterial
Output
B
n
L
H
X
O
n
L
H
Z
© 2001 Fairchild Semiconductor Corporation
DS011349
www.fairchildsemi.com

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