74VCX00M datasheet, PDF - EEWORLD Datasheet

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74VCX00M: DescriptionLow Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs; Categorylogic logic; File Size513KB，10 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74VCX00M Overview

Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs

74VCX00M Parametric

Parameter Name	Attribute value
Brand Name	Fairchild Semiconduc
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	SOIC
package instruction	SOP, SOP14,.25
Contacts	14
Manufacturer packaging code	14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY
Reach Compliance Code	compli
ECCN code	EAR99
series	ALVC/VCX/A
JESD-30 code	R-PDSO-G14
JESD-609 code	e3
length	8.6235 mm
Load capacitance (CL)	30 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	RAIL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	2.8 ns
propagation delay (tpd)	37 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.753 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
Base Number Matches	1

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74VCX00 Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs

July 1999

Revised February 2005

74VCX00

Low Voltage Quad 2-Input NAND Gate

with 3.6V Tolerant Inputs and Outputs

General Description

The VCX00 contains four 2-input NAND gates. This prod-

uct is designed for low voltage (1.2V to 3.6V) V

applica-

tions with I/O compatibility up to 3.6V.

The VCX00 is fabricated with an advanced CMOS technol-

ogy to achieve high-speed operation while maintaining low

CMOS power dissipation.

Features

1.2V to 3.6V V

supply operation

3.6V tolerant inputs and outputs

2.8 ns max for 3.0V to 3.6V V

Power-off high impedance inputs and outputs

Static Drive (I

)

24 mA @ 3.0V V

Uses patented noise/EMI reduction

circuitry

Latchup performance exceeds JEDEC 78 conditions

ESD performance:

Human body model

2000V

Machine model

250V

Leadless Pb-Free DQFN package

Ordering Code:

Order Number

74VCX00M

74VCX00BQX

(Note 1)

74VCX00MTC

74VCX00MTCX_NL

(Note 2)

Package

Number

M14A

MLP014A

MTC14

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDED J-STD-020B.

Note 1:

DQFN package available in Tape and Reel only.

Note 2:

“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

DS500160

www.fairchildsemi.com

74VCX00M Related Products

	74VCX00M	74VCX00	74VCX00BQX	74VCX00_05	74VCX00MTCX_NL
Description	Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
Is it Rohs certified?	conform to	-	conform to	-	conform to
Maker	Fairchild	-	Fairchild	-	Fairchild
Parts packaging code	SOIC	-	MLP	-	TSSOP
package instruction	SOP, SOP14,.25	-	HVQCCN, LCC14,.1X.12,20	-	TSSOP, TSSOP14,.25
Contacts	14	-	14	-	14
Reach Compliance Code	compli	-	compli	-	compli
series	ALVC/VCX/A	-	ALVC/VCX/A	-	ALVC/VCX/A
JESD-30 code	R-PDSO-G14	-	R-XQCC-N14	-	R-PDSO-G14
JESD-609 code	e3	-	e4	-	e3
length	8.6235 mm	-	3 mm	-	5 mm
Load capacitance (CL)	30 pF	-	30 pF	-	30 pF
Logic integrated circuit type	NAND GATE	-	NAND GATE	-	NAND GATE
MaximumI(ol)	0.024 A	-	0.024 A	-	0.024 A
Humidity sensitivity level	1	-	1	-	1
Number of functions	4	-	4	-	4
Number of entries	2	-	2	-	2
Number of terminals	14	-	14	-	14
Maximum operating temperature	85 °C	-	85 °C	-	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-	-40 °C
Package body material	PLASTIC/EPOXY	-	UNSPECIFIED	-	PLASTIC/EPOXY
encapsulated code	SOP	-	HVQCCN	-	TSSOP
Encapsulate equivalent code	SOP14,.25	-	LCC14,.1X.12,20	-	TSSOP14,.25
Package shape	RECTANGULAR	-	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE	-	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	RAIL	-	TAPE AND REEL	-	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	-	260	-	260
power supply	3.3 V	-	3.3 V	-	3.3 V
Prop。Delay @ Nom-Su	2.8 ns	-	2.8 ns	-	2.8 ns
propagation delay (tpd)	37 ns	-	37 ns	-	37 ns
Certification status	Not Qualified	-	Not Qualified	-	Not Qualified
Schmitt trigger	NO	-	NO	-	NO
Maximum seat height	1.753 mm	-	0.8 mm	-	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	1.2 V	-	1.2 V	-	1.2 V
Nominal supply voltage (Vsup)	1.5 V	-	1.5 V	-	1.5 V
surface mount	YES	-	YES	-	YES
technology	CMOS	-	CMOS	-	CMOS
Temperature level	INDUSTRIAL	-	INDUSTRIAL	-	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	-	Nickel/Palladium/Gold (Ni/Pd/Au)	-	Matte Tin (Sn)
Terminal form	GULL WING	-	NO LEAD	-	GULL WING
Terminal pitch	1.27 mm	-	0.5 mm	-	0.65 mm
Terminal location	DUAL	-	QUAD	-	DUAL
Maximum time at peak reflow temperature	30	-	NOT SPECIFIED	-	NOT SPECIFIED
width	3.9 mm	-	2.5 mm	-	4.4 mm
Base Number Matches	1	-	1	-	1

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