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74VCX38: DescriptionLow Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs; File Size512KB，10 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs

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74VCX38 Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs

July 1999

Revised February 2005

74VCX38

Low Voltage Quad 2-Input NAND Gate with

Open Drain Outputs and

3.6V Tolerant Inputs and Outputs

General Description

The VCX38 contains four 2-input NAND gates with open

drain outputs. This product is designed for low voltage

(1.2V to 3.6V) V

applications with I/O compatibility up to

3.6V.

The VCX38 is fabricated with advanced CMOS technology

to achieve high-speed operation while maintaining CMOS

low power dissipation.

Features

1.2V to 3.6V V

supply operation

3.6V tolerant inputs and outputs

2.8 ns max for 3.0V to 3.6V V

Power-Off high impedance inputs and outputs

Static Drive (I

)

24 mA @ 3.0V V

Uses patented Quiet Series

noise/EMI reduction

circuitry

Latchup performance exceeds JEDEC 78 conditions

ESD performance:

Human body model

2000V

Machine model

250V

Leadless Pb-Free DQFN package

Ordering Code:

Order Number

74VCX38M

74VCX38BQX

(Note 1)

74VCX38MTC

74VCX38MTCX_NL

Package

Number

M14A

MLP014A

MTC14

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1:

DQFN package available in Tape and Reel.

Quiet Series

is a trademark of Fairchild Semiconductor Corporation.

DS500161

www.fairchildsemi.com

74VCX38 Related Products

	74VCX38	74VCX38BQX	74VCX38M	74VCX38_05	74VCX38MTCX_NL	74VCX38MTC
Description	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs
Is it Rohs certified?	-	conform to	conform to	-	conform to	conform to
Maker	-	Fairchild	Fairchild	-	Fairchild	Fairchild
Parts packaging code	-	QFN	SOIC	-	TSSOP	TSSOP
package instruction	-	2.50 X 3 MM, MO-241AA, DQFN-14	0.150 INCH, MS-012, SOIC-14	-	4.40 MM, LEAD FREE, MO-153AB, TSSOP-14	4.40 MM, MO-153AB, TSSOP-14
Contacts	-	14	14	-	14	14
Reach Compliance Code	-	compli	unknow	-	_compli	unknow
series	-	ALVC/VCX/A	ALVC/VCX/A	-	ALVC/VCX/A	ALVC/VCX/A
JESD-30 code	-	R-XQCC-N14	R-PDSO-G14	-	R-PDSO-G14	R-PDSO-G14
JESD-609 code	-	e3	e3	-	e3	e3
length	-	3 mm	8.6235 mm	-	5 mm	5 mm
Load capacitance (CL)	-	30 pF	30 pF	-	30 pF	30 pF
Logic integrated circuit type	-	NAND GATE	NAND GATE	-	NAND GATE	NAND GATE
MaximumI(ol)	-	0.024 A	0.024 A	-	0.024 A	0.024 A
Humidity sensitivity level	-	1	1	-	1	1
Number of functions	-	4	4	-	4	4
Number of entries	-	2	2	-	2	2
Number of terminals	-	14	14	-	14	14
Maximum operating temperature	-	85 °C	85 °C	-	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C	-	-40 °C	-40 °C
Output characteristics	-	OPEN-DRAIN	OPEN-DRAIN	-	OPEN-DRAIN	OPEN-DRAIN
Package body material	-	UNSPECIFIED	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	HVQCCN	SOP	-	TSSOP	TSSOP
Encapsulate equivalent code	-	LCC14,.1X.12,20	SOP14,.25	-	TSSOP14,.25	TSSOP14,.25
Package shape	-	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	-	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	-	TAPE AND REEL	RAIL	-	TAPE AND REEL	RAIL
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	260	-	260	260
power supply	-	3.3 V	3.3 V	-	3.3 V	3.3 V
Prop。Delay @ Nom-Su	-	2.8 ns	2.8 ns	-	2.8 ns	2.8 ns
propagation delay (tpd)	-	33.5 ns	33.5 ns	-	33.5 ns	33.5 ns
Certification status	-	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Schmitt trigger	-	NO	NO	-	NO	NO
Maximum seat height	-	0.8 mm	1.753 mm	-	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	-	3.6 V	3.6 V	-	3.6 V	3.6 V
Minimum supply voltage (Vsup)	-	1.2 V	1.2 V	-	1.2 V	1.2 V
Nominal supply voltage (Vsup)	-	1.5 V	1.5 V	-	1.5 V	1.5 V
surface mount	-	YES	YES	-	YES	YES
technology	-	CMOS	CMOS	-	CMOS	CMOS
Temperature level	-	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
Terminal surface	-	Tin (Sn)	Matte Tin (Sn)	-	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	-	NO LEAD	GULL WING	-	GULL WING	GULL WING
Terminal pitch	-	0.5 mm	1.27 mm	-	0.65 mm	0.65 mm
Terminal location	-	QUAD	DUAL	-	DUAL	DUAL
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	-	2.5 mm	3.9 mm	-	4.4 mm	4.4 mm
Base Number Matches	-	1	1	-	1	1

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