HMP8117
NTSC/PAL Video Decoder
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FN4643
Rev 4.00
July 29, 2009
The HMP8117 is a high quality NTSC and PAL video
decoder with internal A/D converters. It is compatible with
NTSC M, PAL B, D, G, H, I, M, N, and combination N (N
C
)
video standards.
Both composite and S-video (Y/C) input formats are
supported. A 2-line comb filter plus a user-selectable
chrominance trap filter provide high quality Y/C separation.
User adjustments include brightness, contrast, saturation,
hue, and sharpness.
Vertical blanking interval (VBI) data, such as Closed
Captioning, Wide Screen Signalling and Teletext, may be
captured and output as BT.656 ancillary data. Closed
Captioning and Wide Screen Signalling information may also
be read out via the I
2
C interface.
The Videolyzer™ feature provides approved Macrovision
™
copy-protection bypass and detection.
Features
• (M) NTSC and (B, D, G, H, I, M, N, N
C
) PAL Operation
- Optional Auto Detect of Video Standard
- ITU-R BT.601 (CCIR601) and Square Pixel Operation
• Videolyzer Feature
- Macrovision™ Bypass and Detection
• Digital Anti-Alias Filter
• Power Down Mode
• Digital Output Formats
- VMI Compatible
- 8-bit, 16-bit 4:2:2 YCbCr
- 15-bit (5, 5, 5), 16-bit (5, 6, 5) RGB
- Linear or Gamma-Corrected
- 8-bit BT.656
• Analog Input Formats
- Three Analog Composite Inputs
- Analog Y/C (S-video) Input
Ordering Information
PART NUMBER
HMP8117CN
HMP8117CNZ
(Note 1)
PART
MARKING
HMP8117CN
TEMP
RANGE
(°C)
PACKAGE
PKG
DWG. #
• “Raw” (Oversampled) VBI Data Capture
• “Sliced” VBI Data Capture Capabilities
- Closed Captioning
- Widescreen Signalling (WSS)
- BT.653 System B, C and D Teletext
- North American Broadcast Teletext (NABTS)
- World System Teletext (WST)
• 2-Line (1H) Comb Filter Y/C Separator
• Fast I
2
C Interface
• Pb-Free Plus Anneal Available (RoHS Compliant)
0 to +70 80 Ld PQFP Q80.14x20
(Note 2)
HMP8117CNZ 0 to +70 80 Ld PQFP Q80.14x20
(Note 2)
(Pb-free)
HMPVIDEVAL/ISA Evaluation Board: ISA Frame Grabber (Note 3)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. PQFP is also known as QFP and MQFP.
3. Evaluation Board descriptions are in the Applications section.
Applications
• Multimedia PCs
• Video Conferencing
• Video Compression Systems
• Video Security Systems
• LCD Projectors and Overhead Panels
• Related Products
- NTSC/PAL Encoders: HMP8156, HMP8170
FN4643 Rev 4.00
July 29, 2009
Page 1 of 45
FN4643 Rev 4.00
July 29, 2009
Page 2 of 45
Functional Block Diagram
HMP8117
SEE ANALOG FRONT END BLOCK DIAGRAM
SEE DIGITAL PROCESSING BLOCK DIAGRAM
EXTERNAL
ANTI-ALIAS
FILTER
Y
OUT
Y
IN
MACROVISION
DETECT
VBI
DETECTION &
DECODING LOGIC
CVBS1
CVBS2
CVBS3(Y)
COMPOSITE/LUMA
CHROMA
INPUT CLAMP,
MUX,
COARSE AGC,
DC-RESTORE
ADC
YIN[7:0]
P[15:0]
HSYNC
FINE AGC,
DC-RESTORE
CONTROL
INPUT
SAMPLE
RATE
CONVERTER
Y/C
SEPARATION
AND
USER
ADJUSTS
OUTPUT
SAMPLE
RATE
CONVERTER
OUTPUT VSYNC
TIMING
BLANK
AND
DATA
FIELD
FIFO
DVALID
LCAP
EXTERNAL
ANTI-ALIAS
FILTER
C
COARSE AGC
DC-RESTORE
ADC
CIN[7:0]
VBIVALID
CCAP
SYNC-TIP, BACKPORCH TIMING
MICROPROCESSOR
INTERFACE AND
CONTROL
RESET INTREQ
SA
SCL
SCL
FN4643 Rev 4.00
July 29, 2009
Page 3 of 45
Analog Front End Block Diagram
(EXTERNAL)
INPUT
VIDEO
(INTERNAL CLAMP)
VAA
1.75V
nmos
#
PIN
+
GAIN CONTROL
SET POINT
13
4 TO 13
DECODER
4
11
GAIN
CORRECTION
LOGIC
LOW-PASS
FILTER
(REMOVE Fsc)
BACKPORCH
ENABLE
HMP8117
1.0F
75
-
TO
MUX
50A
CHROMA
ATTEN
(BELOW)
7
6
5
CLAMP
CLAMP
CLAMP
1.75V
REF
MUX
SELECT
VID1
VID2
Y_IN
75 75
75
1.0F
1.0F
1.0F
CVBS1
CVBS2
CVBS3(Y)
CHROMA MULT.
(BELOW)
Y
OUT
2X
9
Y
IN
8
FINE ADJUST MULT. FACTOR
2.5V
8-BIT
TRUNCATE
M
U
X
13-STEP
VARIABLE
ATTENUATOR
1.75V
EXTERNAL
ANTI-ALIAS
FILTER
BUF
10-BIT 10
ADC
1.5V
DIGITAL
ANTI-
ALIAS
FILTER
DISABLE
Y[7:0]
CORRECTION
MULTIPLIER
CHARGE PUMP
100A
DISCHARGE
CHARGE
100A
SYNC-TIP ENABLE
2.5V
LCAP
STORAGE
CAP
CHROMA INPUT
C_IN
75
1.0F
EXTERNAL
ANTI-ALIAS
FILTER
C
0.1F
76
(OFFSET LUMA SIGNAL TO LOWER ADC REF ~= 1.5V)
CHROMA
ATTEN
LUMA
DC-RESTORE
LOGIC
CHROMA
MULT.
8-BIT
TRUNCATE
DIGITAL
ANTI-
ALIAS
FILTER
DISABLE
C[7:0]
19
(SIGNAL BIAS ~ 2.0V)
13-STEP
VARIABLE
ATTENUATOR
2.0V
A/D_TEST
2X
17
BUF
10-BIT 10
ADC
1.5V
CORRECTION
MULTIPLIER
CHARGE PUMP
100A
DISCHARGE
CCAP
STORAGE
CAP
0.1F
29
(OFFSET CHROMA SIGNAL TO ADC MID-SCALE ~= 2.0V)
100A
CHARGE
CHROMA
DC-RESTORE
LOGIC
POWERDOWN
SYNC-TIP ENABLE
#
DECODER PIN #
BIAS/
INTERNAL
REFERENCE
28
78
RSET
12.1k
REF_CAP
1.0F
PIN #
5
6
9
7
8
19
17
NOMINAL (NTSC) OPERATING CONDITION
CVBSX. SIZE = INPUT. SYNC TIP CLAMPED AT ~= 1.75 VDC.
Y
OUT
/Y
IN
. SIZE = ~1.0 V
P-P
, SYNC TIP OFFSET ~= 1.5 VDC.
C. SIZE = INPUT SIZE. PORCH OFFSET ~= 2.0 VDC.
A/D_TEST. SIZE ~= F(LUMA AGC), PORCH OFFSET ~= 2.0VDC.
PIN # NOMINAL (NTSC) OPERATING CONDITION
76
29
28
78
LCAP. DC-SIGNAL OFFSET ~= 2.4 VDC.
CCAP. DC-SIGNAL OFFSET ~= 2.4 VDC.
RSET. DC-SIGNAL OFFSET ~= 1.2 VDC.
REF_CAP. DC-SIGNAL OFFSET ~= 2.5 VDC.
FN4643 Rev 4.00
July 29, 2009
Page 4 of 45
Digital Processing Block Diagram
HMP8117
CLK2 FREQ SELECT
(24.54, 27.0 or 29.5MHz)
HUE
ADJUST
LOCK
STATUS
CHROMA
PHASE
DETECTOR
FIELD AND
VSYNC
TO FIFO
LINE LOCKED
PLL LOOP
FILTER
CHROMA
PLL NCO
CHROMA
PLL LOOP
FILTER
LINE LOCKED
NCO
CLK2 TO
4FSC RATIO
4FSC
CLOCK
C[7:0]
M
U
X
C, CVBS
INPUT
SAMPLE
RATE
CONVERTER
LINE
DELAY
COMB
FILTER
CHROMA
DEMOD
CHROMA DATA
CHROMA
AGC AND
SATURATION
ADJUST
U, V
VSYNC
DETECT
U/V TO CbCr
COLOR SPACE
CONVERTER,
COLOR KILLER
CHROMA
LP FILTER
CbCr
SYNC
STRIPPER,
BRIGHTNESS DATA OUTPUT
TIMING
AND
AND
CONTRAST
TIMING
DATA
ADJUST,
FIFO
RGB
CONVERSION
P[15:0]
HSYNC
VSYNC
BLANK
FIELD
DVALID
VBIVALID
ENABLE
CHROMA
TRAP
HORIZONTAL
AND VERTICAL
SHARPNESS
ADJUST
OUTPUT
SAMPLE
RATE
CONVERTER
Y[7:0]
Y
LUMA DATA
M
U
X
NORMAL
LP FILTER
M
U
X
Y
VBI STATUS
SHARPNESS
ADJUST
FILTER
SELECT
STANDARD
SELECT
VBI DETECTION
AND DECODING LOGIC
MACROVISION
DETECT
MV STATUS
HMP8117
Introduction
The HMP8117 is designed to decode baseband composite
or S-video NTSC and PAL signals, and convert them to
either digital YCbCr or RGB data. In addition to performing
the basic decoding operations, these devices include
hardware to decode different types of VBI data and to
generate full-screen blue, black and color bar patterns.
Digital PLLs are used to synchronize to all NTSC and PAL
standards. A chroma PLL is used to maintain color lock for
chroma demodulation while a line-locked PLL is used to
maintain vertical spatial alignment. The PLLs are designed
to maintain lock in the presence of VCR head switches, VCR
trick-mode and multi-path noise.
The HMP8117 provides the Videolyzer feature for
Macrovision (MV) copy-protection bypass and detection.
Digitization of Video
Prior to A/D conversion, the input signal is offset and scaled to
known video levels. After digitization, sample rate converters
and a comb filter are used to perform color separation and
demodulation.
A/D Conversion
Each CVBSX video input channel has a video clamp circuit
that is independent of PLL timing. The input clamp provides
a coarse signal offset to position the sync tip within the A/D
converter sampling range so that the AGC and DC-
RESTORE logic can operate.
A/D Conversion
Video data is sampled at the CLK2 frequency then processed
by the input sample rate converter. The output levels of the
ADC after AGC and DC restoration processing are:
(M) NTSC
(M, N) PAL
white
black
blank
sync
196
66
56
0
(B, D, G, H, I, N
C
)
PAL
196
59
59
0
External Video Processing
Before a video signal can be digitized the decoder has some
external processing considerations that need to be
addressed. This section discusses those external aspects of
the HMP8117.
Analog Video Inputs
The HMP8117 supports either three composite or two
composite and one S-video input.
Three analog video inputs (CVBS 1-3) are used to select
which one of three composite video sources are to be
decoded. To support S-video applications, the Y channel
drives the CVBS3(Y) analog input, and the C channel drives
the C analog input.
The analog inputs must be AC-coupled to the video signals,
as shown in the Applications section.
AGC and DC Restoration
The AGC amplifier attenuates or amplifies the analog video
signal to ensure that the blank level generates code 56 or 59
depending on the video standard. The difference from the
ideal blank level of 56 or 59 is used to control the amount of
attenuation or gain of the analog video signal. To obtain a
stable DC reference for the AGC, a digital low-pass filter
removes the chroma burst from the input signal’s backporch.
DC restoration positions the video signal so that the sync tip
generates a code 0. The internal timing windows for AGC
and DC restoration are show in Figure 3. The appropriate
windows are automatically determined by the decoder when
the input signal is auto-detected or manually selected.
Anti-alias Filters
Although a 23 tap digital halfband anti-alias filter is provided
for each A/D channel, an external passive filter is
recommended for optimum performance. The digital filter
has a flat response out to 5.4MHz with an approximate -3dB
bandwidth of 6.3MHz using a 27MHz input CLK2 sample
rate. For the CVBSx inputs, the filter is connected between
the YOUT and YIN pins. For the C (chroma) input, the anti-
alias filter should be connected before the C input.
Recommended filter configurations are shown on the
reference schematic in Figure 20. These filters have flat
response out to 4.2MHz with an approximate -3dB
bandwidth of 8MHz. If upgrading from the HMP8115 or
HMP8112A, the previous filter configurations may be used
but with slightly degraded bandwidth. Alternative higher or
lower performance filters configurations may substituted.
VIDEO INPUT
AGC
DC RESTORE
FIGURE 1. AGC AND DC RESTORE INTERNAL TIMING
FN4643 Rev 4.00
July 29, 2009
Page 5 of 45
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