DATASHEET
ISL5416
Four-Channel Wideband Programmable DownConverter
The ISL5416 Four-Channel Wideband Programmable Digital
DownConverter (WPDC) is designed for high dynamic range
applications such as cellular basestations where the
processing of multiple channels is required in a small
physical space. The WPDC combines four channels in a
single package, each including: an NCO, a digital mixer,
digital filters, an AGC and a resampling filter.
All channels are independently programmable and may be
updated in real time. Each of the four channels can select
any of the four digital input buses. Each of the tuners can
process a W-CDMA channel. Channels may be cascaded or
polyphased for increased bandwidth. Selectable outputs
include I samples, Q samples, and AGC gain. Outputs from
the part are available over the parallel, serial or uP
interfaces.
FN6006
Rev 3.00
Aug 2004
Features
• Up to 95MSPS Input
• Four Parallel 16-bit Fixed or 17-bit Floating Point Inputs
• Programmable RF Attenuator/VGA Control
• 32-Bit Programmable Carrier NCO with > 110dB SFDR
• 20-bit Internal Data Path
• Filter Functions
- Multi-Stage Cascaded-Integrator-Comb (CIC) Filter
- Two programmable FIR Filters (first up to 32-taps,
second up to 64-taps)
- Half Band Interpolation Filter
- Resampling FIR Filter
• Overall decimation from 1 to >4096
• Digital AGC with up to 96dB of Gain Range
• Up to Four Independent 16-bit Parallel Outputs
• Serial Output Option
• 16-bit Parallel
P
Interface
• 1.8V core, 3.3V I/O Operation
• Evaluation Board and Configuration Software available
• Pb-free available
Ordering Information
PART
NUMBER
ISL5416KI
ISL5416KIZ
(See Note)
ISL5416EVAL1
TEMP
RANGE (
o
C)
-40 to 85
-40 to 85
25
PACKAGE
256 BGA
256 BGA
(Pb-free)
PKG. DWG. #
V256.17x17
V256.17x17
EVALUATION KIT
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which is
compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Applications
• Basestation Receivers: GSM/EDGE, CDMA2000, UMTS.
Block Diagram
TEST
REGISTER
OUTPUT
RANGE CONTROL
AOUT(15:8)
INPUT CHANNEL ROUTING
NCO I
MIXER
CIC
Q
FIR1
FILTER
I
Q
FIR2
FILTER
I
AGC
Q
Q
I
IHBF
Q
I
RESAMPLER
Q
I
OUTPUT ROUTING & FORMATTING
AOUT(7:0)
FSYNCA
OEA
AIN(16:0)
ENIA
CLKA
INPUT
SELECT
CLOCK &
FORMAT
INPUT A
INPUT B
INPUT C
INPUT D
CHANNEL O
CHANNEL 1
CHANNEL 2
CHANNEL 3
CLKO1
CLKO2
/INTRPT
EOUT(15:0)
RF ATTENUATOR
VGA CONTROL
JTAG
SYNCHRONIZATION
SYNCO SYNCIN1 SYNCIN2
P
INTERFACE
ADD(2:0)
uP MODE
CE
RD or
RD/WR
FN6006 Rev 3.00
Aug 2004
P(15:0)
RESET
WR or
DSTRB
Page 1 of 71
TYPICAL CHANNEL
FILTER
CASCADE
OUTPUT
24
/
24
/
24
20
GAIN / FIR /
20 2 24
/
/
x1, 2, 4, 8
ROUND
SATURATE
1-64 TAPS
R=1-8
BYPASS
24
AGC /
24
/
0 - 96 dB
BYPASS
R
O 16
/
U 16
N /
D
F
I
F
O
24
/
SELECT
FORMAT
/
24
16
16
16
/ IHBF / RESAMPLING /
16
16
16
FILTER
/
/
/
MUX
CASCADE
INPUTS
AIN(16:0)
BIN(16:0)
CIN(16:0)
DIN(16:0)
TEST INPUT
DIGITAL 24
16 TUNING /
/
MIXER 24
/
CIC
24
FILTER /
24
/
24
20
/ GAIN / FIR
24
20 1
/
/
x1, 2, 4, 8
ROUND
SATURATE
MUX
MUX
NCO
1-5 STAGES
R=2-64K
BYPASS
1-32 TAPS
R=1-8
BYPASS
32-BIT CONTROL
>110 db SFDR
INPUT A
AIN(16:0)
ENIA
CLKA
INPUT
FORMAT
RANGE
CONTROL
TEST
REGISTER
MUX
CHANNEL 0
CASCADE
IN
DIGITAL
TUNER
OUTPUT
FORMAT
SLOT CONTROL
CH 0, 1 MUXING
AOUT(15:0)
FSYNCA
OEA
EXT AGC CNTRL
CASCADE
OUT
INPUT B
BIN(16:0)
ENIB
CLKB
INPUT
FORMAT
RANGE
CONTROL
MUX
CHANNEL 1
AGC GAIN
BOUT(15:0)
OUTPUT MULTIPLEXING
MUX
DIGITAL
TUNER
OUTPUT
FORMAT
SLOT CONTROL
CH 0, 1 MUXING
FSYNCB
OEB
TO SERIAL TO PARALLEL
TO uP
SEQUENCING
INTERFACE ROUTING
AND ROUTING
CLKC
RANGE
CONTROL
MUX
CLKD
RANGE
CONTROL
MUX
FN6006 Rev 3.00
Aug 2004
Page 2 of 71
ISL5416
ISL5416
CHANNEL 2
INPUT C
CIN(16:0)
ENIC
INPUT
FORMAT
COUT(15:0)
FSYNCC
OEC
DIGITAL
TUNER
OUTPUT
FORMAT
SLOT CONTROL
CH 2, 3 MUXING
INPUT D
DIN(16:0)
ENID
INPUT
FORMAT
CHANNEL 3
AGC GAIN
DOUT(15:0)
DIGITAL
TUNER
OUTPUT
FORMAT
SLOT CONTROL
CH 2, 3 MUXING
SERIAL OUTPUTS
SEQUENCED uP READ DATA
JTAG
SYNCHRONIZATION
uP INTERFACE
P(15:0), uPMODE, RD (RD/WR),
WR (DSTRB), CE, ADD(2:0)
SYNCO SYNCIN1 SYNCIN2
FSYNCD
OED
CLKO1
CLKO2/
INTRPT
MUX
EOUT(15:0)
TRST
TMS
TCLK
TDI
TDO
RESET
ISL5416
256-LEAD BGA
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
Ain9
B
Ain8
C
Ain7
D
Ain6
E
Ain5
F
Ain3
G
Ain2
H
Ain0
J
CLKC
K
GND
L
Cin14
M
Cin12
N
Cin10
P
Cin9
R
GND
T
Din8
Din7
Din5
ENIC
Cin2
CE
Eout0
Cout0
Cout2
OEC
Cout4
VccIO FSYNCD Dout8
Cout9
Din9
Vcc
Din6
ENID
Din2
Din1
Eout1
Dout1
Dout2
Vcc
Dout5
Dout6
Dout7
Dout9
GND
Cin11
Din10
Din11
Din4
Din3
Vcc
Din0
Dout0
P1
OED
Dout4
GND
VccIO Dout10 Cout10
Cin13
Din12
Din13
GND
GND
WR
RD
Vcc
P0
Dout3
Add0
Dout11 Dout12 Cout12 Cout11
Cin15
Eout3
Din15
Din14
TRST
Add2
GND
Add1
GND
P2
Vcc
Cin16
Din16
Eout4
Eout5
Eout2
P3
P4
Dout15 CLKO2/ CLKO1 Cout15
INTRPT
Dout13 Dout14 Cout14 Cout13
VccIO
CLKD
Eout6
Eout7
GND
GND
P5
P6
Bout0
VccIO Aout0
Bin0
Vcc
Eout8
Eout9
GND
P7
Bout1
Bout2
Aout1
Aout2
Ain1
Bin1
Bin2
TMS
TDI
P8
GND
Bout3
Aout3
Vcc
RESET
Vcc
Bin3
GND
GND
GND
uPmode
GND
P10
P9
Bout5
Bout4
VccIO
Aout4
Aout5
Ain4
Bin4
Bin5
Eout10 Bin13 Eout11
Vcc
P13
P11
TDO
GND
Bout6
Bout7 Aout6
Aout7
Bin6
Bin7
GND
Bin14
Bin15
Eout12 Eout14
P14
P12
Bout15 Bout14
Bout8
Bout9 Aout8
Aout9
Bin8
ENIB
Bin11
Bin12
Ain13
Bin16
CLKB
P15
VccIO
OEB
VccIO FSYNCB VccIO Bout10 Aout10
Bin9
Bin10
Vcc
Vcc
Ain15
Ain16
Eout15
GND SYNCIn2
OEA
Vcc
Bout13 Bout12 Bout11 FSYNCA
ENIA
Ain10
Ain11
Ain12
Ain14
Eout13
CLKA SYNCIn1 SYNCO Aout15 Aout14 Aout13
GND
Aout12 Aout11
Cin8
Cin7
Cin6
Cin5
Cin4
Cin3
Cin1
Cin0
Cout1
TCLK
Cout3
Cout5
Cout6 FSYNCC Cout7
Cout8
POWER PIN
GROUND PIN
SIGNAL PIN
THERMAL BALL
NC (NO CONNECTION)
Vcc = +1.8V CORE SUPPLY VOLTAGE
VccIO = +3.3V I/O SUPPLY VOLTAGE
NOTE: Thermal Balls should be connected to the ground plane
Unused Input Balls should be connected to ground or V
cc
IO as appropriate
FN6006 Rev 3.00
Aug 2004
Page 3 of 71
ISL5416
Pin Descriptions
NAME
TYPE
INTERNAL
PULL-UP/DOWN
DESCRIPTION
POWER SUPPLY
Vcc
VccIO
GND
INPUTS
Ain(16:0)
Bin(16:0)
Cin(16:0)
Din(16:0)
ENIA
I
I
I
I
I
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
Parallel Data Input bus A. Sampled on the rising or falling edge (programmable) of clock when ENIA
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Parallel Data Input bus B. Sampled on the rising or falling edge (programmable) of clock when ENIB
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Parallel Data Input bus C. Sampled on the rising or falling edge (programmable) of clock when ENIC
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Parallel Data Input bus D. Sampled on the rising or falling edge (programmable) of clock when ENID
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
-
-
-
Positive Power Supply Voltage (core), 1.8V
0.09
Positive Power Supply Voltage (I/O), 3.3V
0.165
Ground, 0V.
ENIB
I
PULL DOWN
ENIC
I
PULL DOWN
ENID
I
PULL DOWN
CONTROL
CLKA
CLKB
CLKC
CLKD
SYNCIn1
I
I
I
I
I
PULL DOWN
PULL DOWN
PULL DOWN
PULL DOWN
Input clock for data bus A. CLKA or CLKC may be used for Ain(16:0).
Input clock for data bus B. CLKB or CLKC may be used for Bin(16:0).
Input clock for data bus C. CLKC is also the master clock for all channels of ISL5416
Input clock for data bus D. CLKD or CLKC may be used for Din(16:0).
Global synchronization input signal 1. SYNCIn1 can update the carrier NCOs, reset decimation
counters, restart the filter, and restart the output section among other functions. For most of the
functional blocks, the response to SYNCIn1 is programmable and can be enabled or disabled.
Global synchronization input signal 2. SYNCIn2 can update the carrier NCOs, reset decimation
counters, restart the filter, and restart the output section among other functions. For most of the
functional blocks, the response to SYNCIn2 is programmable and can be enabled or disabled.
Synchronization Output Signal. The processing of multiple ISL5416 devices can be synchronized by
tying the SYNCO from one ISL5416 device (the master) to the SYNCIn of all the ISL5416 devices
(the master and slaves). An optional internal SYNCO to SYNCInX connection is provided.
PULL UP
Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default
values.
SYNCIn2
I
PULL DOWN
SYNCO
O
RESET
I
FN6006 Rev 3.00
Aug 2004
Page 4 of 71
ISL5416
Pin Descriptions
NAME
JTAG
TDO
TDI
TMS
TCLK
TRST
O
I
I
I
I
TYPE
(Continued)
DESCRIPTION
INTERNAL
PULL-UP/DOWN
Test data out
PULL UP
PULL UP
PULL DOWN
PULL UP
Test data in.
Test mode select.
Test clock.
Test reset. Active low. If JTAG not used, tie this pin low. If there is a trace connected to the pin and
there is enough board noise, the JTAG port might get into an unexpected state and stop
communications with the part
OUTPUTS
Aout(15:0)
O
Parallel Data Output bus A. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section. See Table 24.
Parallel Data Output bus B. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Parallel Data Output bus C. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Parallel Data Output bus D. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Below is the table of the serial output bits allocation for DOUT.
SERIAL OUTPUT BITS ALLOCATION
SER. OUTPUT A SER. OUTPUT B SER. OUTPUT C SER. OUTPUT D
SCLKX *
SSYNCX *
SD1X *
SD2X *
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
DOUT15
Bout(15:0)
O
Cout(15:0)
O
Dout(15:0)
O
* X denotes A, B, C, D as appropriate
Eout(15:0)
CLKO1
CLKO2/
INTRPT
O
O
O
A 16-bit parallel VGA/Attenuator control output. Partitionable into separate 4 or 8-bit busses.
Output Clock 1. Can be programmed to be at CLKC/N for N = 1 to 16. The polarity of CLKO1 is
programmable.
Available ONLY on Rev B (final) version of the part. Provides a complementary output or a second
clock to simplify board routing. Polarity is programmable. It can also be programmed as an interrupt
from one or more channels for a sequenced read (FIFO-like) mode.
See register GWA = 0000h, bit
13.
FN6006 Rev 3.00
Aug 2004
Page 5 of 71
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