ISL5217_05 datasheet, PDF - EEWORLD Datasheet

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ISL5217_05: DescriptionQuad Programmable Up Converter; File Size2MB，43 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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ISL5217_05 Overview

Quad Programmable Up Converter

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DATASHEET

ISL5217

Quad Programmable Up Converter

The ISL5217 Quad Programmable UpConverter (QPUC) is a

QASK/FM modulator/FDM upconverter designed for high

dynamic range applications such as cellular basestations. The

QPUC combines shaping and interpolation filters, a complex

modulator, and timing and carrier NCOs into a single package.

Each QPUC can create four FDM channels. Multiple QPUCs can

be cascaded digitally to provide for up to 16 FDM channels in

multi-channel applications.

The ISL5217 supports both vector and FM modulation. In vector

modulation mode, the QPUC accepts 16-bit I and Q samples to

generate virtually any quadrature AM or PM modulation format.

The QPUC also has two FM modulation modes. In the FM with

pulse shaping mode, the 16-bit frequency samples are pulse

shaped/bandlimited prior to FM modulation. No band limiting filter

follows the FM modulator. This FM mode is useful for GMSK

type modulation formats. In the FM with band limiting filter mode,

the 16-bit frequency samples directly drive the FM modulator.

The FM modulator output is filtered to limit the spectral

occupancy. This FM mode is useful for analog FM or FSK

modulation formats.

The QPUC includes an NCO driven interpolation filter, which

allows the input and output sample rate to have an integer

and/or variable relationship. This re-sampling feature

simplifies cascading modulators with sample rates that do not

have harmonic or integer frequency relationships.

The QPUC offers digital output spectral purity that exceeds

100dB at the maximum output sample rate of 104MSPS, for

input sample rates as high as 6.5MSPS.

A 16-bit microprocessor compatible interface is used to load

configuration and baseband data. A programmable FIFO depth

interrupt simplifies the interface to the I and Q input FIFOs.

FN6004

Rev. 3.00

July 8, 2005

Features

• Output Sample Rates Up to 104MSPS with Input Data

Rates Up to 6.5MSPS

• Processing Capable of >140dB SFDR Out of Band

• Vector modulation for supporting IS-136, EDGE, IS95, TD-

SCDMA, CDMA-2000-1X/3X, W-CDMA, and UMTS

• FM Modulation for Supporting AMPS, NMT, and GSM

• Four Completely Independent Channels on Chip, Each With

Programmable 256 Tap Shaping FIR, Half-Band, and High

Order Interpolation Filters

• 16-Bit parallel

Processor

Interface and Four Independent

Serial Data Inputs

• Two 20-bit I/O Buses and Two 20-bit Output Buses Allow

Cascading Multiple Devices

• 32-Bit Programmable Carrier NCO; 48-Bit Programmable

Symbol Timing NCOs

• Dynamic Gain Profiling and Output Routing Control

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Single or Multiple Channel Digital Software Radio

Transmitters (Wide-Band or Narrow-Band)

• Base Station Transmitter and Smart Antennas

• Operates with HSP50216 in Software Radio Solutions

• Compatible with the HI5960/ISL5961 or HI5828/ISL5929

D/A Converters

Ordering Information

PART

NUMBER

ISL5217KI

ISL5217KIZ (Note)

ISL5217EVAL1

TEMP

RANGE (

-40 to 85

PACKAGE

196 Ld BGA

Evaluation Kit

PKG. DWG.

V196.15x15

196 Ld BGA (Pb-free) V196.15x15

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate termination finish,

which are RoHS compliant and compatible with both SnPb and Pb-free soldering

operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Block Diagram

INPUT I/Q SHAPING I/Q

DATA

FILTER/

FM MOD.

I/Q HALF I/Q INTPL I/Q COMPLEX I/Q

MIXER

BAND

FILTER

SIN

COS

CARRIER

NCO

GAIN CONTROL

GAIN PROFILE

SDA

SDB

SDC

SDD

Q0 4 CH

I1 SUM

SAMPLE

NCO



DELAY

SUM

CAS IOUT(19:0)

SUM

CAS

SUM QOUT(19:0)

QIN(19:0)

IIN(19:0)

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

P<15:0>

A<6:0>

{CNTRL}



PARALLEL HOST INTERFACE

CONFIGURATION AND CONTROL BUS

FN6004 Rev. 3.00

July 8, 2005

Page 1 of 43

ISL5217

Pin Descriptions (all signals are active high unless otherwise stated)

NAME

POWER SUPPLY

VCCC

VCCIO

GND

CLK

RESET

P<15:0>

A<6:0>

RDMODE

I/O

Positive Device Core Power Supply Voltage, 2.5V

0.125V.

Positive Device Input/Output Power Supply Voltage, 3.3V

0.165V.

Ground, 0V

Input Clock. All processing in the ISL5217 occurs on the rising edge of CLK.

Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, halting all processing.

Data bus. Bit 15 is the MSB.

Address bus. Bit 6 is the MSB.

Chip Select. (active low). Enables device to respond to

P

access.

NOTE: See Appendix A, Errata Sheet.

Read Mode. Read mode selects the Read/Write mode for the Microprocessor Interface. When low the device is

configured for separate RD and WR strobe inputs. When high the device is configured for a common Read/Write

and Data Strobe inputs. Internally pulled down.

Write Strobe, (active low). Dual function input. The input is configured for Write Strobe when RDMODE is low. When

RDMODE is high the input is configured for Data Strobe.

Write Strobe. The data on P<15:0> is written to the destination selected by A<6:0> on the rising edge of WR when

CS is asserted (low).

Data Strobe. The data on P<15:0> is written to the destination selected by A<6:0> on the rising edge of Data strobe

when RD is low and CS is asserted (low) or read from the address selected by A<6:0> placed on P<15:0> when

RD is high and CS is asserted (low).

Read Strobe (Active Low). Dual function input. The input is configured for Read Strobe when RDMODE is low.

When RDMODE is high the input is configured for Read/Write Strobe.

Read Strobe. The data at the address selected by A(6:0) is placed on P<15:0> when RD is asserted (low) and

CS is asserted (low).

Read/Write Strobe. Determines the type of

P

access.

Offset Binary. When set to 1, the output data bus format is offset binary. When set to 0 the output data bus format

is 2’s complement.

Output Three-state Control. OUTEN<1:0> is decoded to provide three-state control of the output data buses. When

TRITST is asserted, the three-state control divides the 80-bit output into eight groups of 10-bits each. When TRITST

is deasserted, the three-state control operates on the 20-bit real and imaginary cascade out data buses.

Tester Three-State Control. This signal determines how the OUTEN<1:0> is decoded to provide the necessary

three-state controls when in normal or tester applications. Set low for normal operation.

Serial Data A-D. (SDX) Serial Data Input for the I and Q vectors. The processing channel selected for this data will

shift the data in on the rising edge of its serial TX clock. The data vectors are shifted in with the MSB first.

SERIAL CLK A-D. (SCLKX) Dual function output. The output is SERIAL CLK when symbol data is input through

the serial data port. When symbol data is input through the

P

port the output is SAMPLE CLK 0-3. The polarity of

SCLKX is programmable.

Serial Clock. Programmable rate clock signal provided to the data source to shift serial data out. Programmed rates

can be CLK/(1-32), or 32x sample clock. See control word 0x17, bit 15 for shut-off conditioning.

SAMPLE CLK. Signal provided to the data source to indicate when data is being transferred from the FIFO to the

shaping filter. The SAMPLE CLK output is generated by the sample rate NCO and has approximately 50% duty

cycle. The sample is taken on the high-to-low transition.

FRAME STROBE A-D. (FSRX) Multiple Function Output. When control word 0x0c, bit 11 is set to zero, the output

is FRAME STROBE when symbol data is input through the serial data port. When symbol data is input through the

P

port the output is FIFO READY 0-3. When control word 0x0c, bit 11 is set to one, the setting of the

FSRMode<1:0> bits in indirect address 0x407 determine the output. The polarity of FSRX is programmable.

FRAME STROBE. Signal provided to the data source to initiate a serial word transfer. Alternatively selectable

through Serial Control 0x11, bit 14 to be Epoch frame strobe. Epoch is a pre-carry out of the fixed integer divider

instead of the serial frame strobe. The Epoch pre-carry out is six clocks ahead of the true carry out and can be used

to synchronize fixed integer dividers of other devices. See control word 0x17, bit 15 for shut-off conditioning.

FIFO READY. Indicates the I and Q FIFO pointer is less than the programmed FIFO depth.

UPDX or TXENX: When 0x0c, bit 11 is set to one, and FSRMode<1:0> is set to 10, the internal channel UPDX is

output. When 0x0c, bit 11 is set to one, and FSRMode<1:0> is set to 11, the internal channel TXENX is output. See

Table 43 for additional details.

TYPE

DESCRIPTION

MICROPROCESSOR INTERFACE AND CONTROL

OFFBIN

OUTEN<1:0>

TRITST

SERIAL DATA / SYNCHRONIZATION AND FIFO STATUS

SDA, SDB,

SDC, SDD

SCLKA,

SCLKB,

SCLKC,

SCLKD

FSRA,

FSRB,

FSRC,

FSRD

FN6004 Rev. 3.00

July 8, 2005

Page 4 of 43

ISL5217

Pin Descriptions (all signals are active high unless otherwise stated)

NAME

TXENA,

TXENB,

TXENC,

TXEND

TYPE

DESCRIPTION

(Continued)

Transmit Enable A-D. (TXENX) The processing channel selected for this enable will force a channel flush

(conditioned by control word 0x0c, bit 2), clear the data RAMs, and update the selected configuration registers upon

assertion. No additional requests for serial data will be made when TXENX is deasserted, unless conditioned by

control word 0x0c, bit 3. The polarity of TXENX is programmable. Optionally, TXENX can be internally generated

with a programmable duty cycle. Two different programmable TXENX cycles can be programmed and toggled

between based on programmed cycle length. See control word 0x0c, bit 11 and Table 43 for additional details.

Update A-D. (UPDX) The processing channel selected for this input updates the selected configuration registers, if

the associated update mask bit is set. The polarity of UPDX is programmable.

Synchronization Output. The processing of multiple ISL5217 devices can be synchronized through software by

connecting the SYNCO of the master ISL5217 device to an UPDX pin of the ISL5217 slaves. The polarity of SYNCO

is programmable.

Output Data Bus A (19:0). Output bus A contains the digital modulated QUC output samples from Output

Summer/Formatter 1. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.

Output Data Bus B (19:0). The output bus contains the digital modulated QUC output samples from Output

Summer/Formatter 2. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.

I Cascade In (19:0) or OUTPUT BUS C. Dual function I/O bus. The bus is configured for input when the output mode

is cascade in. The bus is configured for output for all other output modes.

I Cascade In. Input bus allows multiple parts to be cascaded by routing the digital modulated signal I CAS OUT,

(Bus A), from one QUC into Output Summer/Formatter 1 of a second QUC. I CAS IN (19:0) is in 2’s complement

format and is sampled on the rising edge of CLK. Bit<19> is the MSB.

Output Data Bus C. The output bus contains the digital modulated QUC output samples from Output

Summer/Formatter 3. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.

Q Cascade in (19:0) or Output Data Bus D. Dual function I/O bus. The bus is configured for input when the output

mode is cascade in. The bus is configured for output for all other output modes.

Q Cascade in. Input bus allows multiple parts to be cascaded by routing the digital modulated signal Q CAS OUT,

(Bus B), from one QUC into Output Summer/Formatter 2 of a second QUC. Q CAS IN (19:0) is in 2’s complement

format and is sampled on the rising edge of CLK. Bit<19> is the MSB.

Output Data Bus D. The output bus contains the digital modulated QUC output samples from Output

Summer/Formatter 4. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.

I data strobe. (active high). Used in the muxed I/Q mode. When asserted, the output data buses contain valid I data.

JTAG Test Mode Select. Internally pulled up.

JTAG Test Data In. Internally pulled up.

JTAG Test Clock.

JTAG Test Reset (Active Low). Internally pulled-up. This pin should be driven by the JTAG logic to obtain a TAP

controller reset, or if JTAG is not utilized, this pin should be tied to ground for normal operation. As recommended

in the 1149.1 standard documentation the TRST test pin should be made active soon after power-up to guarantee

a known state within the TAP logic on the ISL5217. This avoids potential damage due to signal contention at the

circuit’s inputs and outputs.

JTAG Test Data Out.

UPDA, UPDB,

UPDC, UPDD

SYNCO

MODULATED DATA (80)

IOUT(19:0)

QOUT(19:0)

IIN(19:0)

I/O

QIN(19:0)

I/O

ISTRB

TMS

TDI

TCK

TRST

JTAG TEST ACCESS PORT

TDO

FN6004 Rev. 3.00

July 8, 2005

Page 5 of 43

ISL5217_05 Related Products

	ISL5217_05	ISL5217	ISL5217KI	ISL5217KIZ	ISL5217EVAL1
Description	Quad Programmable Up Converter	Quad Programmable Up Converter	Quad Programmable Up Converter	Quad Programmable Up Converter	Quad Programmable Up Converter

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