NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
D
P50N02LS
TO-263 (D
2
PAK)
PRODUCT SUMMARY
V
(BR)DSS
25
R
DS(ON)
12mΩ
I
D
55A
G
S
1. GATE
2. DRAIN
3. SOURCE
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Avalanche Current
Avalanche Energy
Repetitive Avalanche Energy
Power Dissipation
2
1
SYMBOL
V
GS
LIMITS
±20
55
38
150
36
250
8.6
85
46
-55 to 150
275
UNITS
V
T
C
= 25 °C
T
C
= 100 °C
I
D
I
DM
I
AR
A
L = 0.1mH
L = 0.05mH
T
C
= 25 °C
T
C
= 100 °C
E
AS
E
AR
P
D
T
j
, T
stg
T
L
mJ
W
Operating Junction & Storage Temperature Range
Lead Temperature ( /
16
” from case for 10 sec.)
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Case
Junction-to-Ambient
Case-to-Heatsink
1
2
1
°C
SYMBOL
R
θJC
R
θJA
R
θCS
TYPICAL
MAXIMUM
2.3
62.5
UNITS
°C / W
0.6
Pulse width limited by maximum junction temperature.
Duty cycle
≤
1％
ELECTRICAL CHARACTERISTICS (T
C
= 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
V
GS
= 0V, I
D
= 250µA
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 0V, V
GS
= ±20V
V
DS
= 20V, V
GS
= 0V
V
DS
= 20V, V
GS
= 0V, T
C
= 125 °C
25
0.8
1.2
2.5
±250
25
250
nA
µA
V
LIMITS
UNIT
MIN TYP MAX
1
MAY-24-2001
NIKO-SEM
1
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
I
D(ON)
R
DS(ON)
1
P50N02LS
TO-263 (D
2
PAK)
On-State Drain Current
Drain-Source On-State
1
Resistance
V
DS
= 10V, V
GS
= 10V
V
GS
= 7V, I
D
= 20A
V
GS
= 10V, I
D
= 30A
V
DS
= 15V, I
D
= 40A
DYNAMIC
55
13
12
16
16
15
A
mΩ
S
Forward Transconductance
g
fs
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
2
2
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
2
1400
V
GS
= 0V, V
DS
= 15V, f = 1MHz
380
200
40
V
DS
= 0.5V
(BR)DSS
, V
GS
= 10V,
I
D
= 30A
12
25
9
V
DS
= 15V, R
L
= 1Ω
I
D
≅
35A, V
GS
= 10V, R
GS
= 2.5Ω
150
20
30
nS
nC
pF
Gate-Source Charge
Gate-Drain Charge
2
2
Turn-On Delay Time
Rise Time
t
d(on)
t
r
Turn-Off Delay Time
Fall Time
2
2
t
d(off)
t
f
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T
C
= 25 °C)
Continuous Current
Pulsed Current
3
1
I
S
I
SM
V
SD
t
rr
I
RM(REC)
Q
rr
I
F
= I
S
, dl
F
/dt = 100A /
µS
I
F
= I
S
, V
GS
= 0V
70
200
0.043
55
170
1.3
A
V
nS
A
µC
Forward Voltage
Reverse Recovery Time
Peak Reverse Recovery Current
Reverse Recovery Charge
1
2
Pulse test : Pulse Width
≤
300
µsec,
Duty Cycle
≤
2％.
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P50N02LS”, DATE CODE or LOT #
2
MAY-24-2001
NXP MCU
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