DATASHEET
ISL6209
High Voltage Synchronous Rectified Buck MOSFET Driver
The ISL6209 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology in mobile
computing applications. This driver, combined with an Intersil
Multi-Phase Buck PWM controller, such as ISL6216, ISL6244,
and ISL6247, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
The ISL6209 features 4A typical sink current for the lower gate
driver. The 4A typical sink current is capable of holding the
lower MOSFET gate during the PHASE node rising edge to
prevent the shoot-through power loss caused by the high dv/dt
of the PHASE node. The operation voltage matches the 30V
breakdown voltage of the MOSFETs commonly used in mobile
computer power supplies.
The ISL6209 also features a three-state PWM input that,
working together with most of Intersil multiphase PWM
controllers, will prevent a negative transient on the output
voltage when the output is being shut down. This feature
eliminates the Schottky diode, that is usually seen in a
microprocessor power system for protecting the
microprocessor, from reversed-output-voltage damage.
The ISL6209 has the capacity to efficiently switch power
MOSFETs at frequencies up to 2MHz. Each driver is capable of
driving a 3000pF load with a 8ns propagation delay and less
than a 10ns transition time. This product implements
bootstrapping on the upper gate with an internal bootstrap
Schottky diode, reducing implementation cost, complexity, and
allowing the use of higher performance, cost effective
N-Channel MOSFETs. Programmable dead-time with gate
threshold monitoring is integrated to prevent both MOSFETs
from conducting simultaneously.
FN9132
Rev.2.00
Mar 23, 2007
Features
• Drives Two N-Channel MOSFETs
• Shoot-Through Protection
- Active gate threshold monitoring
- Programmable dead-time
• 30V Operation Voltage
• 0.4 On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast output rise time
- Propagation delay 8ns
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Voltage Supplies for Intel and AMD® Mobile
Microprocessors
• High Frequency Low Profile DC/DC Converters
• High Current Low Output Voltage DC/DC Converters
• High Input Voltage DC/DC Converter
Ordering Information
PART
NUMBER
ISL6209CB*
PART
MARKING
ISL6209CB
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
M8.15
M8.15
L8.3x3
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
• Technical Brief TB447 “Guidelines for Preventing Boot-to-
Phase Stress on Half-Bridge MOSFET Driver ICs”
-10 to +100 8 Ld SOIC
ISL6209CBZ* ISL6209CBZ -10 to +100 8 Ld SOIC
(Note)
(Pb-free)
ISL6209CR*
209C
-10 to +100 8 Ld 3x3 QFN
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN9132 Rev.2.00
Mar 23, 2007
Page 1 of 10
ISL6209
Pinouts
ISL6209
(8 LD SOIC)
TOP VIEW
UGATE
BOOT
PWM
GND
1
2
3
4
8
7
6
5
PHASE
DELAY
VCC
LGATE
BOOT 1
PWM 2
3
GND
4
LGATE
t
FU
6
6 DELAY
5 VCC
ISL6209
(8 LD QFN)
TOP VIEW
PHASE
7
UGATE
8
ISL6209 Block Diagram
VCC
DELAY
BOOT
UGATE
PWM
10K
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
VCC
PHASE
LGATE
GND
THERMAL PAD (FOR QFN PACKAGE ONLY)
FIGURE 1. BLOCK DIAGRAM
Timing Diagram
2.5V
PWM
t
PDHU
t
PDLU
t
RU
t
RU
t
PTS
1V
UGATE
LGATE
1V
t
FL
t
PDLL
t
PDHL
t
FL
t
RL
t
TSSHD
t
TSSHD
t
FU
t
PTS
FN9132 Rev.2.00
Mar 23, 2007
Page 2 of 10
ISL6209
Typical Application - Two Phase Converter Using ISL6209 Gate Drivers
V
BAT
+5V
+5V
VCC
+5V
FB
VCC
VSEN
PGOOD
PWM1
PWM2
PWM
DELAY
DRIVE
ISL6209
PHASE
LGATE
COMP
BOOT
UGATE
+V
CORE
MAIN
CONTROL
VID
ISEN1
ISEN2
+5V
V
BAT
VCC
FS
DACOUT
GND
PWM
DELAY
DRIVE
ISL6209
BOOT
UGATE
PHASE
LGATE
FIGURE 2. TYPICAL APPLICATION
FN9132 Rev.2.00
Mar 23, 2007
Page 3 of 10
ISL6209
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V
DELAY
, V
PWM
) . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (V
BOOT-GND
). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
BOOT To PHASE Voltage (V
BOOT-PHASE
) . . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage (Note 1) . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V
GND - 8V (<20ns Pulse Width, 10J)
UGATE Voltage . . . . . . . . . . . . . . . . V
PHASE
- 0.3V (DC) to V
BOOT
V
PHASE
- 5V (<20ns Pulse Width, 10J) to V
BOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
SOIC Package (Note 2) . . . . . . . . . . . .
110
N/A
QFN Package (Notes 3, 4). . . . . . . . . .
80
15
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-10°C to +100°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . +125°C
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
2.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
POR Rising
POR Falling
Hysteresis
BOOTSTRAP DIODE
Forward Voltage
PWM INPUT
Input Current
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
PWM pin floating, V
VCC
= 5V
-
-
2.2
-
85
3.4
2.9
500
-
4.2
-
-
A
V
V
mV
V
F
V
VCC
= 5V, forward bias current = 2mA
0.40
0.52
0.60
V
I
PWM
V
PWM
= 5V
V
PWM
= 0V
-
-
-
3.1
-
250
-250
-
-
150
-
-
1.8
-
-
A
A
V
V
ns
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Hold-off Time
SWITCHING TIME
UGATE Rise Time (Note 5)
LGATE Rise Time (Note 5)
UGATE Fall Time (Note 5)
LGATE Fall Time (Note 5)
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
t
RUGATE
t
RLGATE
t
FUGATE
t
FLGATE
t
PDLUGATE
t
PDLLGATE
V
VCC
= 5V
V
VCC
= 5V
V
VCC
= 5V, temperature = +25°C
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, No Output Load, DELAY = VCC
V
VCC
= 5V, No Output Load, DELAY = VCC
-
-
-
-
-
-
8
8
8
4
13
13
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
FN9132 Rev.2.00
Mar 23, 2007
Page 4 of 10
ISL6209
Electrical Specifications
PARAMETER
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
OUTPUT
Upper Drive Source Resistance
Upper Driver Source Current (Note 5)
Upper Drive Sink Resistance
Upper Driver Sink Current (Note 5)
Lower Drive Source Resistance
Lower Driver Source Current (Note 5)
Lower Drive Sink Resistance
Lower Driver Sink Current (Note 5)
NOTE:
5. Guaranteed by characterization, not 100% tested in production.
R
UGATE
I
UGATE
R
UGATE
I
UGATE
R
LGATE
I
LGATE
R
LGATE
I
LGATE
500mA Source Current
V
UGATE-PHASE
= 2.5V
500mA Sink Current
V
UGATE-PHASE
= 2.5V
500mA Source Current
V
LGATE
= 2.5V
500mA Sink Current
V
LGATE
= 2.5V
-
-
-
-
-
-
-
-
1.0
2.0
1.0
2.0
1.0
2.0
0.4
4.0
2.5
-
2.5
-
2.5
-
1.0
-
A
A
A
A
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
t
PDHUGATE
t
PDHLGATE
TEST CONDITIONS
V
VCC
= 5V, Outputs Unloaded,
DELAY = VCC
V
VCC
= 5V, Outputs Unloaded,
DELAY = VCC
MIN
10
10
TYP
20
20
MAX
30
30
UNITS
ns
ns
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to the
gate of high-side power N-Channel MOSFET.
DELAY (Pin 7 for SOIC-8, Pin 6 for QFN)
The DELAY pin sets the dead-time between gate switching for
the ISL6209. Connect a resistor to GND from this pin to adjust
the dead-time, refer to Figure 4. Tie this pin to VCC to disable
the delay circuitry. See
Shoot-Through Protection
section for
more detail.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a return
path for the upper gate driver.
Description
Operation
Designed for speed, the ISL6209 dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one externally
provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
PDLLGATE
], the lower gate begins to fall. Typical fall
times [t
FLGATE
] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the LGATE
voltage and determines the upper gate delay time
[t
PDHUGATE
], based on how quickly the LGATE voltage drops
below 1V. This prevents both the lower and upper MOSFETs
from conducting simultaneously, or shoot-through. Once this
delay period is completed, the upper gate drive begins to rise
[t
RUGATE
], and the upper MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
PDLUGATE
] is encountered before the
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500k resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
FN9132 Rev.2.00
Mar 23, 2007
Page 5 of 10
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