CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTE:
3.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
W option
U option
MIN
TYP
(Note 1)
10
50
-20
I
DCP
= 1mA
T = -40°C to +85°C
V-
V- = -5.5V; V
CC
= +5.5V,
wiper current = (V
CC
-V-)/R
TOTAL
70
10/10/
25
Voltage at pins; V- to V
CC
0.1
1
±50
V
CC
200
+20
MAX
UNIT
kΩ
kΩ
%
ppm/°C
V
Ω
pF
µA
PARAMETER
R
H
to R
L
resistance
R
H
to R
L
resistance tolerance
TC
R
Resistance Temperature Coefficient
(Notes 12, 13)
R
H
,R
L
R
W
C
H
/C
L
/C
W
I
LkgDCP
R
H
,R
L
terminal voltage
Wiper resistance
Potentiometer Capacitance (Note 13)
Leakage on R
H
, R
L
, R
W
pins
VOLTAGE DIVIDER MODE
(V- @ R
L
; V
CC
@ R
H
; Voltage at R
W
= V
RW
unloaded)
INL
(Note 6)
DNL
(Note 5)
ZSerror
(Note 3)
FSerror
(Note 4)
TC
V
(Notes 7, 13)
Integral non-linearity
Differential non-linearity
Zero-scale error
W, U options
W option
U option
Full-scale error
W option
U option
Ratiometric Temperature Coefficient
DCP Register set at 63d,
T = -40°C to +85°C
-1
-0.5
0
0
-4
-2
1
0.5
-1
-1
±4
1
0.5
4
2
0
0
LSB
(Note 6)
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
ppm/°C
RESISTOR MODE
(Measurements between R
W
and R
L
with R
H
not connected, or between R
W
and R
H
with R
L
not connected)
RINL
(Note 11)
RDNL
(Note 10)
Roffset
(Note 9)
Integral non-linearity
Differential non-linearity
Offset
DCP register set between 20 hex and 7F hex.
Monotonic over all tap positions
W and U options
DCP Register set to 00 hex, W option
DCP Register set to 00 hex, U option
-1
-0.5
0
0
2
0.5
1
0.5
5
2
MI
(Note 8)
MI
(Note 8)
MI
(Note 8)
3
FN8241.3
September 5, 2006
ISL95711
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
I
V-1
I
CC2
I
V-2
I
CCSB
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
200
-100
200
-3
1
1
-5
-2
-10
1
-2.5
2.5
0.2
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby
state
3
10
UNITS
µA
µA
µA
mA
µA
µA
µA
µA
µA
µs
V
V
V/ms
ms
V
CC
supply current, volatile write/read f
SCL
= 400kHz;SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
V- supply current, volatile write/read
V
CC
supply current, non volatile write
V- supply current, nonvolatile write
V
CC
current (standby)
f
SCL
= 400kHz;SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Nonvolatile Write State only)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Nonvolatile Write State only)
V
CC
= +5.5V, I
2
C Interface in Standby State
V
CC
= +3.6V, I
2
C Interface in Standby State
V- = -5.5V, I
2
C Interface in Standby State
V- = -3.6V, I
2
C Interface in Standby State
I
V-SB
V- current (standby)
I
LkgDig
t
DCP
(Note 13)
Vpor
Leakage current, at pins SDA, SCL,
A0, and A1
DCP wiper response time
Power-on recall for both V- and V
CC
Voltage at pin from GND to V
CC
SCL falling edge of last bit of DCP Data Byte to
wiper change
V-
V
CC
V-Ramp
t
D
(Note 13)
V- ramp rate
Power-up delay
EEPROM SPECS
EEPROM Endurance
EEPROM Retention
SERIAL INTERFACE SPECS
V
IL
V
IH
Hysteresis
V
OL
Cpin
(Note 15)
f
SCL
t
IN
t
AA
t
BUF
A0, A1, SDA, and SCL input buffer
LOW voltage
A0, A1, SDA, and SCL input buffer
HIGH voltage
SDA and SCL input buffer hysteresis
SDA output buffer LOW voltage,
sinking 4mA
A0, A1, SDA, and SCL pin capacitance
SCL frequency
Pulse width suppression time at SDA
and SCL inputs
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
Clock LOW time
Clock HIGH time
START condition setup time
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
1300
-0.3
0.7*V
CC
0.05*
V
CC
0
0.4
10
400
50
900
0.3*V
CC
V
CC
+
0.3
V
V
V
V
pF
kHz
ns
ns
ns
Temperature
≤
+75°C
200,000
50
Cycles
Years
t
LOW
t
HIGH
t
SU:STA
1300
600
600
ns
ns
ns
4
FN8241.3
September 5, 2006
ISL95711
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HD:STO
t
DH
t
R
(Note 15)
t
F
(Note 15)
Cb
(Note 15)
Rpu
(Note 15)
t
WC
(Notes 14)
t
SU:A
t
HD:A
NOTES:
1. Typical values are for T
A
= +25°C and
±
5V supply voltage.
2. LSB: [V(RW)
127
– V(RW)
0
]
/
127. V(RW)
127
and V(RW)
0
are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = (V(RW)
0
– V-)/LSB.
4. FS error = [V(RW)
127
– V
CC
]
/
LSB.
5. DNL = [V(RW)
i
– V(RW)
i-1
]
/
LSB-1, for i = 1 to 127. i is the DCP register setting.
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