www.fairchildsemi.com
FSDL0365RN, FSDM0365RN
Features
• Internal Avalanche Rugged Sense FET
• Consumes only 0.65W at 240VAC & 0.3W load with
Advanced Burst-Mode Operation
• Frequency Modulation for EMI Reduction
• Precision Fixed Operating Frequency
• Internal Start-up Circuit
• Pulse-by-Pulse Current Limiting
• Abnormal Over Current Protection (AOCP)
• Over Voltage Protection (OVP)
• Over Load Protection (OLP)
• Internal Thermal Shutdown Function (TSD)
• Auto-Restart Mode
• Under Voltage Lockout (UVLO)
• Low Operating Current (3mA)
• Adjustable Peak Current Limit
• Built-in Soft Start
Green Mode Fairchild Power Switch (FPS
TM
)
effective flyback converters.
OUTPUT POWER TABLE
230VAC
±15%
(3)
PRODUCT
FSDL321
FSDH321
FSDL0165RN
FSDM0265RN
FSDH0265RN
FSDL0365RN
FSDM0365RN
FSDL321L
FSDH321L
FSDL0165RL
FSDM0265RL
FSDH0265RL
FSDL0365RL
FSDM0365RL
Adapt-
er
(1)
11W
11W
13W
16W
16W
19W
19W
11W
11W
13W
16W
16W
19W
19W
Open
Frame
(2)
17W
17W
23W
27W
27W
30W
30W
17W
17W
23W
27W
27W
30W
30W
85-265VAC
Adapt-
er
(1)
8W
8W
11W
13W
13W
16W
16W
8W
8W
11W
13W
13W
16W
16W
Open
Frame
(2)
12W
12W
17W
20W
20W
24W
24W
12W
12W
17W
20W
20W
24W
24W
Applications
• SMPS for VCR, SVR, STB, DVD & DVCD Player
• SMPS for Printer, Facsimile & Scanner
• Adapter for Camcorder
Related Application Notes
• AN-4137, 4141, 4147(Flyback) / AN-4134(Forward)
Description
Each product in the FSDx0365RN (x for L, M) family consists
of an integrated Pulse Width Modulator (PWM) and Sense
FET, and is specifically designed for high performance off-line
Switch Mode Power Supplies (SMPS) with minimal external
components. Both devices are integrated high voltage power
switching regulators which combine an avalanche rugged
Sense FET with a current mode PWM control block. The inte-
grated PWM controller features include: a fixed oscillator with
frequency modulation for reduced EMI, Under Voltage Lock
Out (UVLO) protection, Leading Edge Blanking (LEB), an
optimized gate turn-on/turn-off driver, Thermal Shut Down
(TSD) protection, Abnormal Over Current Protection (AOCP)
and temperature compensated precision current sources for
loop compensation and fault protection circuitry. When com-
pared to a discrete MOSFET and controller or RCC switching
converter solution, the FSDx0365RN devices reduce total
component count, design size, weight while increasing effi-
ciency, productivity and system reliability. Both devices pro-
vide a basic platform that is well suited for the design of cost-
FPS
TM
is a trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
Notes:
1. Typical continuous power in a non-ventilated enclosed
adapter with sufficient drain pattern as a heat sinker, at
50°C ambient.
2. Maximum practical continuous power in an open frame
design with sufficient drain pattern as a heat sinker, at 50°C
ambient.
3. 230 VAC or 100/115 VAC with doubler.
Typical Circuit
AC
IN
DC
OUT
Vstr
Ipk
PWM
Vfb
Drain
Vcc
Source
Rev.1.0.8
FSDL0365RN, FSDM0365RN
Figure 1. Typical Flyback Application
Internal Block Diagram
Vcc
2
+
Vstr
5
Drain
6,7,8
I
CH
8V/12V
Vcc
V
BURH
-
Vcc good
Freq.
Modulation
OSC
Vref
V
BURL
/V
BURH
I
BUR(pk)
Vcc
I
DELAY
Vcc
I
FB
Internal
Bias
Vfb
3
Normal
PWM
Burst
S
R
Q
Q
2.5R
Ipk
4
Soft
Start
R
Gate
driver
LEB
V
SD
Vcc
Vovp
Vcc good
TSD
R
Q
1 GND
S
Q
AOCP
Vocp
Figure 2. Functional Block Diagram of FSDx0365RN
2
FSDL0365RN, FSDM0365RN
Pin Definitions
Pin Number
1
Pin Name
GND
Pin Function Description
Sense FET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transform-
er winding, current is supplied from pin 5 (Vstr) via an internal switch during
startup (see Internal Block Diagram section). It is not until Vcc reaches the
UVLO upper threshold (12V) that the internal start-up switch opens and de-
vice power is supplied via the auxiliary transformer winding.
The feedback voltage pin is the non-inverting input to the PWM comparator.
It has a 0.9mA current source connected internally while a capacitor and op-
tocoupler are typically connected externally. A feedback voltage of 6V trig-
gers over load protection (OLP). There is a time delay while charging
external capacitor Cfb from 3V to 6V using an internal 5uA current source.
This time delay prevents false triggering under transient conditions, but still
allows the protection mechanism to operate under true overload conditions.
This pin adjusts the peak current limit of the Sense FET. The feedback
0.9mA current source is diverted to the parallel combination of an internal
2.8kΩ resistor and any external resistor to GND on this pin to determine the
peak current limit. If this pin is tied to Vcc or left floating, the typical peak cur-
rent limit will be 2.15A.
This pin connects directly to the rectified AC line voltage source. At start up
the internal switch supplies internal bias and charges an external storage
capacitor placed between the Vcc pin and ground. Once the Vcc reaches
12V, the internal switch is opened.
The drain pins are designed to connect directly to the primary lead of the
transformer and are capable of switching a maximum of 650V. Minimizing
the length of the trace connecting these pins to the transformer will decrease
leakage inductance.
2
Vcc
3
Vfb
4
Ipk
5
Vstr
6, 7, 8
Drain
Pin Configuration
8DIP
8LSOP
GND 1
Vcc 2
Vfb 3
Ipk 4
8 Drain
7 Drain
6 Drain
5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDL0365RN, FSDM0365RN
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Characteristic
Drain Pin Voltage
Vstr Pin Voltage
Drain Current Pulsed
(1)
Single Pulsed Avalanche Energy
(2)
Supply Voltage
Feedback Voltage Range
Total Power Dissipation
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
Symbol
V
DRAIN
V
STR
I
DM
E
AS
V
CC
V
FB
P
D
T
J
T
A
T
STG
Value
650
650
12.0
127
20
-0.3 to V
CC
1.56
Internally limited
-25 to +85
-55 to +150
Unit
V
V
A
mJ
V
V
W
°C
°C
°C
Note:
1. Repetitive rating: Pulse width is limited by maximum junction temperature
2. L = 51mH, starting Tj = 25°C
Thermal Impedance
(Ta=25°C, unless otherwise specified)
Parameter
8DIP
Junction-to-Ambient Thermal
(1)
Junction-to-Case Thermal
(2)
Junction-to-Top Thermal
(3)
Symbol
Value
80.01
18.85
33.70
Unit
°C/W
°C/W
°C/W
θ
JA
θ
JC
ψ
JT
Note:
1. Free standing with no heatsink; Without copper clad.
/ Measurement Condition : Just before junction temperature T
J
enters into OTP.
2. Measured on the DRAIN pin close to plastic interface.
3. Measured on the PKG top surface.
- all items are tested with the standards JESD 51-2 and 51-10 (DIP).
4
FSDL0365RN, FSDM0365RN
Electrical Characteristics
(Ta = 25°C unless otherwise specified)
Parameter
SENSE FET SECTION
Zero-Gate-Voltage Drain Current
Drain-Source On-State Resistance
(1)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
CONTROL SECTION
Switching Frequency
Switching Frequency Modulation
Switching Frequency
Switching Frequency Modulation
Switching Frequency
Maximum Duty Cycle
Minimum Duty Cycle
UVLO Threshold Voltage
Feedback Source Current
Internal Soft Start Time
BURST MODE SECTION
Burst Mode Voltage
PROTECTION SECTION
Peak Current Limit
Current Limit Delay Time
(3)
Thermal Shutdown Temperature
Shutdown Feedback Voltage
Over Voltage Protection
Shutdown Delay Current
Leading Edge Blanking Time
TOTAL DEVICE SECTION
Operating Supply Current
(control part only)
Start-Up Charging Current
Vstr Supply Voltage
I
OP
I
CH
V
STR
V
CC
=14V
V
CC
=0V
V
CC
=0V
1
0.7
35
3
0.85
-
5
1.0
-
mA
mA
V
I
LIM
t
CLD
T
SD
V
SD
V
OVP
I
DELAY
t
LEB
V
FB
=4V
-
Max. inductor current
1.89
-
125
5.5
18
3.5
200
2.15
500
140
6.0
19
5.0
-
2.41
-
-
6.5
-
6.5
-
A
ns
°C
V
V
µA
ns
V
BURH
V
BURL
-
-
0.4
0.25
0.5
0.35
0.6
0.45
V
V
Variation
(2)
f
OSC
∆f
MOD
f
OSC
∆f
MOD
∆f
OSC
D
MAX
D
MIN
V
START
V
STOP
I
FB
t
S/S
V
FB
=GND
V
FB
=GND
V
FB
=GND
V
FB
=4V
FSDM0365R
FSDL0365R
-25°C
≤
Ta
≤
85°C
61
±1.5
45
±1.0
-
71
0
11
7
0.7
10
67
±2.0
50
±1.5
±5
77
0
12
8
0.9
15
73
±2.5
55
±2.0
±10
83
0
13
9
1.1
20
KHz
KHz
KHz
KHz
%
%
%
V
V
mA
ms
I
DSS
R
DS(ON)
C
ISS
C
OSS
C
RSS
t
d(on)
t
r
t
d(off)
t
f
V
DS
=650V, V
GS
=0V
V
DS
=520V, V
GS
=0V,
T
C
=125°C
V
GS
=10V, I
D
=0.5A
V
GS
=0V, V
DS
=25V,
f=1MHz
-
-
-
-
-
-
-
V
DS
=325V, I
D
=1.0A
-
-
-
-
-
3.6
315
47
9
11.2
34
28.2
32
50
200
4.5
-
-
-
-
-
-
-
µA
µA
Ω
Symbol
Condition
Min.
Typ.
Max.
Unit
pF
pF
pF
ns
ns
ns
ns
Note:
1. Pulse test: Pulse width
≤
300us, duty
≤
2%
2. These parameters, although guaranteed, are tested in EDS (wafer test) process
3. These parameters, although guaranteed, are not 100% tested in production
5
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