MM74HC32 Quad 2-Input OR Gate
September 1983
Revised January 2005
MM74HC32
Quad 2-Input OR Gate
General Description
The MM74HC32 OR gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. All gates have buffered outputs
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 10 ns
s
Wide power supply range: 2–6V
s
Low quiescent current: 20
µ
A maximum (74HC Series)
s
Low input current: 1
µ
A maximum
s
Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC32M
MM74HC32MX_NL
MM74HC32SJ
MM74HC32MTC
MM74HC32MTCX_NL
MM74HC32N
MM74HC32N_NL
Package
Number
M14A
M14A
M14D
MTC14
MTC14
N14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
Y
=
A
+
B
(1 of 4)
Top View
© 2005 Fairchild Semiconductor Corporation
DS005132
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MM74HC32
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
600 mW
500 mW
(I
CC
)
Storage Temperature Range (T
STG
)
Recommended Operating
Conditions
Min
2
0
Max
6
V
CC
Units
V
V
−
0.5 to
+
7.0V
−
1.5 to V
CC
+
1.5V Supply Voltage (V )
CC
−
0.5 to V
CC
+
0.5V DC Input or Output Voltage
±
20 mA
(V
IN
, V
OUT
)
±
25 mA Operating Temperature Range (T )
A
±
50 mA Input Rise or Fall Times
−
40
+
85
1000
500
400
°
C
ns
ns
ns
−
65
°
C to
+
150
°
C
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
(Note 4)
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
2.0
4.5
6.0
4.7
5.2
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
T
A
= −40
to 85°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
20
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
| I
OUT
|
≤
4.0 mA
| I
OUT
|
≤
5.2 mA
4.5V
6.0V
2.0V
4.5V
6.0V
V
IN
=
V
IL
| I
OUT
|
≤
4.0 mA
| I
OUT
|
≤
5.2 mA
4.5V
6.0V
6.0V
6.0V
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IL
|I
OUT
|
≤
20
µA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC32
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation
Delay
Conditions
Typ
10
Guaranteed
Limit
18
Units
ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation
Delay
t
TLH
, t
THL
Maximum Output Rise
and Fall Time
C
PD
C
IN
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=
25°C
Typ
30
12
9
30
8
7
50
5
10
100
20
17
75
15
13
T
A
= −40
to 85°C
Guaranteed Limits
125
25
21
95
19
16
Units
ns
ns
ns
ns
ns
ns
pF
(per gate)
10
pF
3
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