XR16L2751IM datasheet, PDF - EEWORLD Datasheet

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XR16L2751IM: DescriptionSerial I/O Controller, 2 Channel(s), 0.78125MBps, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size321KB，52 Pages; ManufacturerExar; Related ProductsFound5parts with similar functions to XR16L2751IM

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XR16L2751IM Overview

Serial I/O Controller, 2 Channel(s), 0.78125MBps, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48

XR16L2751IM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	TFQFP, TQFP48,.35SQ
Contacts	48
Reach Compliance Code	compli
Other features	OPERATES AT 2.5V SUPPLY @ 24 MHZ
Address bus width	4
boundary scan	NO
maximum clock frequency	50 MHz
letter of agreement	ASYNC, BIT
Data encoding/decoding methods	NRZ
Maximum data transfer rate	0.78125 MBps
External data bus width	8
JESD-30 code	S-PQFP-G48
JESD-609 code	e0
length	7 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Encapsulate equivalent code	TQFP48,.35SQ
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	2.5/5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	2.25 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1

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SEPTEMBER 2002

XR16L2751

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.0.0

GENERAL DESCRIPTION

The XR16L2751

(2751) is a low voltage dual

universal asynchronous receiver and transmitter

(UART) with 5 Volt tolerant inputs. The device

includes 2 additional capabilities over the

XR16L2750: Intel and Motorola data bus selection

and a “PowerSave” mode to further reduce sleep

current to a minimum during sleep mode. The 2751’s

XR16C2850 but with added functions. It supports the

Exar’s enhanced features of 64 bytes of TX and RX

FIFOs, programmable FIFO trigger level, FIFO level

counters, automatic hardware and software flow

control, automatic RS-485 half duplex direction

control with programmable turn-around delay, and a

complete modem interface. Onboard registers

provide the user with operational status and data

error tags. An internal loopback capability allows

onboard diagnostics. Independent programmable

baud rate generator is provided in each UART

channel to support data rates up to 6.25 Mbps.

OTE

1 Covered by U.S. Patent #5,649,122 and #5,832,205

FEATURES

•

2.25 to 5.5 Volt Operation

•

5 Volt Tolerant Inputs

•

Functionally Compatible to ST16C2550 and

XR16C2850 with 4 additional inputs

•

Intel or Motorola Data Bus Interface Select

•

Two Independent UARTs

APPLICATIONS

Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt,

and 3 Mbps at 2.5 Volt with 8X sampling rate

64 bytes of Transmit and Receive FIFOs

Transmit and Receive FIFO Level Counters

Programmable TX and RX FIFO Trigger Levels

Automatic Hardware (RTS/CTS) Flow Control

Selectable RTS Flow Control Hysteresis.

Automatic Software (Xoff/Xon) Flow Control

Automatic RS-485 2-wire Half-duplex Direction

Control to the Transceiver via RTS#

Full Modem Interface

Infrared Receive and Transmit Encoder/

decoder

•

Portable and Battery Operated Appliances

•

Wireless Access Servers

•

Ethernet Network Routers

•

Cellular Data Devices

•

Telecommunication Network Routers

•

Factory Automation and Process Controls

IGURE

1. XR16L2751 B

LOCK

IAGRAM

•

PowerSave Feature reduces sleep current to 15 µA

at 3.3 Volt

•

Device Identification

•

Crystal or external clock input

•

Industrial and Commercial Temperature ranges

•

48 TQFP Package (7 x 7 x 1.0 mm)

PwrSave

A2:A0

D7:D0

IOR# (VCC)

IOW# (R/W#)

CSA# (CS#)

CSB# (A3)

INTA (IRQ#)

INTB (logic 0)

TXRDYA#

TXRDYB#

RXRDYA#

RXRDYB#

Reset (Reset#)

16/68#

CLKSEL

HDCNTL#

Intel or

Motorola

Data Bus

Interface

*5 Volt Tolerant Inputs

2.25 to 5.5 Volt VCC

GND

UART Channel A

UART

Regs

BRG

64 Byte TX FIFO

TX & RX

ENDEC

TXA, RXA, DTRA#,

DSRA#, RTSA#,

DTSA#, CDA#, RIA#,

OP2A#

64 Byte RX FIFO

TXB, RXB, DTRB#,

DSRB#, RTSB#,

CTSB#, CDB#, RIB#,

OP2B#

XTAL1

XTAL2

UART Channel B

(same as Channel A)

Crystal Osc/Buffer

2751BLK

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

•

(510) 668-7000

•

FAX (510) 668-7017

•

www.exar.com

XR16L2751

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.0.0

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PIN DESCRIPTIONS

Pin Description

AME

48-TQFP

YPE

ESCRIPTION

DATA BUS INTERFACE

A2:A0

D7:D0

IOR#

(VCC)

26,27,28

3, 2, 1, 48, 47,

46, 45, 44

I/O

Address data lines [2:0]. These 3 address lines select one of the internal registers in

UART channel A/B during a data bus transaction.

Data bus lines [7:0] (bidirectional).

When 16/68# pin is at logic 1, the Intel bus interface is selected and this input

becomes read strobe (active low). The falling edge instigates an internal read cycle

and retrieves the data byte from an internal register pointed by the address lines

[A2:A0], puts the data byte on the data bus to allow the host processor to read it on

the rising edge.

When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is

not used and should be connected to VCC.

When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes

write strobe (active low). The falling edge instigates the internal write cycle and the

rising edge transfers the data byte on the data bus to an internal register pointed by

the address lines.

When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input

becomes read (logic 1) and write (logic 0) signal.

When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel

A in the device.

When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the

Motorola bus interface.

When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel

B in the device.

When 16/68# pin is at logic 0, this input becomes address line A3 which is used for

channel selection in the Motorola bus interface. Input logic 0 selects channel A and

logic 1 selects channel B.

When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel A

interrupt output. The output state is defined by the user through the software setting

of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when

MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1

when MCR[3] is set to a logic 0. See MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device

interrupt output (active low, open drain). An external pull-up resistor is required for

proper operation.

When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel B

interrupt output. The output state is defined by the user and through the software set-

ting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when

MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1

when MCR[3] is set to a logic 0. See MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, this output is not used and

will stay at logic zero level. Leave this output unconnected.

UART channel A Transmitter Ready (active low). The output provides the TX FIFO/

THR status for transmit channel A.

IOW#

(R/W#)

CSA#

(CS#)

CSB#

(A3)

INTA

(IRQ#)

INTB

TXRDYA#

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XR16L2751IM Similar Products

Part Number	Manufacturer	Description
XR16V2751IM	Exar	Serial I/O Controller, 2 Channel(s), 1MBps, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48
XR16M2751IM48-F	Exar	Serial I/O Controller, 1 Channel(s), 1MBps, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, GREEN, TQFP-48
XR16V2751IM-F	Exar	UART Interface IC W/64 BYTE FIFO
XR16L2751CM	Exar	Serial I/O Controller, 2 Channel(s), 0.78125MBps, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48
XR16M2751IM48	Exar	Serial I/O Controller, 1 Channel(s), 1MBps, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48

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