71V2556XSA100BGI8 datasheet, PDF

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71V2556XSA100BGI8: DescriptionZBT SRAM, 128KX36, CMOS, PBGA119, BGA-119; Categorystorage storage; File Size344KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

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71V2556XSA100BGI8 Overview

ZBT SRAM, 128KX36, CMOS, PBGA119, BGA-119

71V2556XSA100BGI8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	2.36 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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128K x 36

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

◆

IDT71V2556S/XS

IDT71V2556SA/XSA

Features

128K x 36 memory configurations

Supports high performance system speed - 166 MHz

(3.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (V

DDQ)

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP) and 119 ball grid array (BGA)

The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBT

, or Zero Bus Turnaround.

Description

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read

or write.

The IDT71V2556 contains data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2556 to be

suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the user

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state two cycles after chip is deselected or a write is

initiated.

The IDT71V2556 has an on-chip burst counter. In the burst mode, the

IDT71V2556 can provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is defined by the

LBO

input pin. The

LBO

pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V2556 SRAMs utilize IDT's latest high-performance CMOS

process and are packaged in a JEDEC standard 14mm x 20mm 100-pin

thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).

Pin Description Summary

-A

, CE

CEN

CLK

ADV/

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Ad d re ss Inp uts

Chip Enab le s

Outp ut Enab le

Re ad /Write Sig nal

Clo ck Enab le

Ind ivid ual Byte Write Se le cts

Clo ck

Ad vance b urst ad d re ss / Lo ad ne w ad d re ss

Line ar / Inte rle ave d Burst Ord e r

Te st Mo d e Se le ct

Te st Data Inp ut

Te st Clo ck

Te st Data Outp ut

JTAG Re se t (Op tio nal)

S le e p Mo d e

Data Inp ut / Outp ut

Co re Po we r, I/O Po we r

Gro und

Inp ut

Outp ut

Inp ut

I/O

Sup p ly

Synchro no us

Asynchro no us

Synchro no us

N/A

Synchro no us

Static

Synchro no us

N/A

Synchro no us

Asynchro no us

Synchro no us

Static

4875 tb l 01

Integrated Device Technology, Inc.

APRIL 2011

DSC-4875/12

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