NC7WZ00 TinyLogic£ UHS Dual 2-Input NAND Gate
April 2000
Revised February 2005
NC7WZ00
TinyLogic£ UHS Dual 2-Input NAND Gate
General Description
The NC7WZ00 is a dual 2-Input NAND Gate from
Fairchild's Ultra High Speed Series of TinyLogic
£
. The
device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while main-
taining low static power dissipation over a broad V
CC
oper-
ating range. The device is specified to operate over the
1.65V to 5.5V V
CC
operating range. The inputs and output
are high impedance when V
CC
is 0V. Inputs tolerate volt-
ages up to 7V independent of V
CC
operating voltage.
Features
s
Space saving US8 surface mount package
s
MicroPak
¥
Pb-Free leadless package
s
Ultra High Speed; t
PD
2.4 ns typ into 50 pF at 5V V
CC
s
High Output Drive;
r
24 mA at 3V V
CC
s
Broad V
CC
Operating Range; 1.65V–5.5V
s
Matches the performance of LCX when operated at
3.3V V
CC
s
Power down high impedance inputs/output
s
Overvoltage tolerant inputs facilitate 5V to 3V translation
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Number
NC7WZ00K8X
NC7WZ00K8X_NL
(Note 1)
NC7WZ00L8X
Package
Number
MAB08A
MAB08A
MAC08A
Code
Top Mark
WZ00
WZ00
N6
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm
Wide
3k Units on Tape and Reel
Package Description
Supplied As
Pb-Free 8-Lead US8, JEDEC MO-187, Variation CA 3k Units on Tape and Reel
3.1mm Wide
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
TinyLogic
£
is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500267
www.fairchildsemi.com
NC7WZ00
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Descriptions
Pin Names
A
n
, B
n
Y
n
Description
Inputs
Output
(Top View)
Pin One Orientation Diagram
Function Table
Y
Inputs
A
L
L
H
H
H
HIGH Logic Level
AAA represents Product Code Top Mark - see ordering code
AB
Output
Y
H
H
H
L
LOW Logic Level
Note:
Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
B
L
H
L
H
L
(Top Thru View)
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2
NC7WZ00
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
DC Input Diode Current (I
IK
)
@V
IN
0.5V
DC Output Diode Current (I
OK
)
@V
OUT
0.5V
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature (T
STG
)
Junction Temperature under Bias (T
J
)
Junction Lead Temperature (T
L
);
(Soldering, 10 seconds)
Power Dissipation (P
D
) @
85
q
C
260
q
C
250 mW
0.5V to
7V
0.5V to
7V
0.5V to
7V
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
150
q
C
Recommended Operating
Conditions
(Note 3)
Supply Voltage Operating (V
CC
)
Supply Voltage Data Retention (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
A
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
@ 1.65V
r
0.15V, 2.5V
r
0.2V
V
CC
@ 3.3V
r
0.3V
V
CC
@ 5.0V
r
0.5V
Thermal Resistance (
T
JA
)
0 ns/V to 20 ns/V
0 ns/V to 10 ns/V
0 ns/V to 5 ns/V
250
q
C/W
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
0V to V
CC
40
q
C to
85
q
C
Note 2:
Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 3:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
V
CC
(V)
1.65 - 1.95
2.3 - 5.5
1.65 - 1.95
2.3 - 5.5
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
V
OL
LOW Level Output Voltage
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
I
IN
I
OFF
I
CC
Input Leakage Current
Power Off Leakage Current
Quiescent Supply Current
0 - 5.5
0.0
1.65 - 5.5
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
1.65
2.3
3.0
4.5
1.52
2.15
2.80
2.68
4.20
0.0
0.0
0.0
0.0
0.08
0.10
0.15
0.22
0.22
0.1
0.1
0.1
0.1
0.24
0.3
0.4
0.55
0.55
Min
0.75 V
CC
0.70 V
CC
0.25 V
CC
0.30 V
CC
1.55
2.2
2.9
4.4
1.69
1.9
2.4
2.3
3.8
0.1
0.1
0.1
0.1
0.24
0.3
0.4
0.55
0.55
V
I
OL
I
OL
I
OL
I
OL
I
OL
4 mA
8 mA
16 mA
24 mA
32 mA
5.5V
V
V
IN
V
IH
I
OL
100
P
A
V
I
OH
I
OH
I
OH
I
OH
I
OH
V
V
IN
V
IL
I
OH
T
A
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
0.75 V
CC
0.70 V
CC
Units
V
Conditions
0.25 V
CC
0.30 V
CC
V
100
P
A
4 mA
8 mA
16 mA
24 mA
32 mA
r
0.1
1
1
r
1.0
10
10
P
A
P
A
P
A
V
IN
V
IN
5.5V, GND
5.5V, GND
V
IN
or V
OUT
3
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NC7WZ00
AC Electrical Characteristics
Symbol
t
PLH
,
t
PHL
Parameter
Propagation Delay
V
CC
(V)
1.8
r
0.15
2.5
r
0.2
3.3
r
0.3
5.0
r
0.5
t
PLH,
t
PHL
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
Propagation Delay
3.3
r
0.3
5.0
r
0.5
0
3.3
5.0
Min
2.0
1.2
0.8
0.5
1.2
0.8
T
A
25
q
C
Typ
5.3
3.2
2.4
1.9
3.0
2.4
2.5
13
17
Max
9.6
5.3
3.7
2.9
4.6
3.6
T
A
40
q
C to
85
q
C
Max
9.8
5.7
4.0
3.2
4.9
3.9
2.0
1.2
0.8
0.5
1.2
0.8
Min
Units
Conditions
Figure
Number
ns
C
L
R
L
C
L
R
L
15 pF,
1 M
:
50 pF,
500
:
Figures
1, 3
ns
pF
pF
Figures
1, 3
(Note 4)
Figure 2
Note 4:
C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at no output
loading and operating at 50% duty cycle. (See Figure 2.) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
(C
PD
)(V
CC
)(f
IN
)
(I
CC
static).
AC Loading and Waveforms
C
L
includes load and stray capacitance
Input PRR
1.0 MHz; t
w
500 ns
FIGURE 1. AC Test Circuit
FIGURE 3. AC Waveforms
Input
PRR
AC Waveform; t
r
t
f
1.8 ns;
50%
10 MHz; Duty Cycle
FIGURE 2. I
CCD
Test Circuit
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4
NC7WZ00
Tape and Reel Specification
Tape Format
Package
Designator
K8X
Carrier
Trailer (Hub End)
TAPE DIMENSIONS
inches (millimeters)
Tape
Section
Leader (Start End)
Number
Cavities
125 (typ)
3000
75 (typ)
Cavity
Status
Empty
Filled
Empty
Cover Tape
Status
Sealed
Sealed
Sealed
TAPE FORMAT for MicroPak
Package
Designator
L8X
Tape
Section
Number
Cavities
125 (typ)
3000
75 (typ)
Cavity
Status
Empty
Filled
Empty
Cover Tape
Status
Sealed
Sealed
Sealed
Leader (Start End)
Carrier
Trailer (Hub End)
TAPE DIMENSIONS
inches (millimeters)
5
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