SN74LS156
Dual 1-of-4 Decoder/
Demultiplexer
The SN74LS156 is a high speed Dual 1-of-4 Decoder/
Demultiplexer. This device has two decoders with common 2-bit
Address inputs and separate gated Enable inputs. Decoder “a” has an
Enable gate with one active HIGH and one active LOW input.
Decoder “b” has two active LOW Enable inputs. If the Enable
functions are satisfied, one output of each decoder will be LOW as
selected by the address inputs. The LS156 has open collector outputs
for wired-OR (DOT-AND) decoding and function generator
applications.
The LS156 is fabricated with the Schottky barrier diode process for
high speed and are completely compatible with all ON Semiconductor
TTL families.
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LS156–OPEN–COLLECTOR
LOW POWER SCHOTTKY
•
•
•
•
•
•
Schottky Process for High Speed
Multifunction Capability
Common Address Inputs
True or Complement Data Demultiplexing
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
16
1
PLASTIC
N SUFFIX
CASE 648
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
V
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Voltage – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
5.5
8.0
Unit
V
°C
V
mA
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS156N
SN74LS156D
Package
16 Pin DIP
16 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
110
December, 1999 – Rev. 0
Publication Order Number:
SN74LS156/D
SN74LS156
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
E
b
15
E
b
14
A
0
13
O
3b
12
O
2b
11
O
1b
10
O
0b
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
E
a
2
E
a
3
A
1
4
O
3a
5
O
2a
6
O
1a
7
O
0a
8
GND
LOADING
(Note a)
PIN NAMES
A
0
, A
1
E
a
, E
b
E
a
O
0
– O
3
Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
1 2
13 3
14 15
E
DECODER a
0
1
2
3
A
0
A
1
A
0
A
1
0
1
E
DECODER b
2
3
7
6
5
4
9
10 11 12
V
CC
= PIN 16
GND = PIN 8
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111
SN74LS156
LOGIC DIAGRAM
E
a
E
a
1
2
13
A
0
A
1
3
14
E
b
E
b
15
7
6
5
4
9
10
11
12
O
0a
O
1a
O
2a
O
3a
O
0b
O
1b
O
2b
O
3b
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with
common Address inputs and separate gated Enable inputs.
When enabled, each decoder section accepts the binary
weighted Address inputs (A
0
, A
1
) and provides four
mutually exclusive active LOW outputs (O
0
– O
3
). If the
Enable requirements of each decoder are not met, all outputs
of that decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (E
a
•E
a
). In demultiplexing
applications, Decoder “a” can accept either true or
complemented data by using the E
a
or E
a
inputs respectively.
The enable gate for Decoder “b” requires two active LOW
inputs (E
b
•E
b
). The LS155 or LS156 can be used as a 1-of-8
Decoder/Demultiplexer by tying E
a
to E
b
and relabeling the
common connection as (A
2
). The other E
b
and E
a
are
connected together to form the common enable.
The LS156 can be used to generate all four minterms of
two variables. These four minterms are useful in some
applications replacing multiple gate functions as shown in
Fig. a. The LS156 has the further advantage of being able to
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A
0
+ A
1
)
⋅
(E + A
0
+ A
1
)
⋅
(E + A
0
+ A
1
)
⋅
(E + A
0
+ A
1
)
where E = E
a
+ E
a
; E = E
b
+ E
b
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
E
A
0
O
0
A
1
E
O
1
A
0
A
1
E
O
2
A
0
A
1
E
O
3
A
0
A
1
O
0
O
1
O
2
O
3
Figure a
TRUTH TABLE
ADDRESS
A
0
X
X
L
H
L
H
A
1
X
X
L
L
H
H
ENABLE “a”
E
a
L
X
H
H
H
H
E
a
X
H
L
L
L
L
O
0
H
H
L
H
H
H
OUTPUT “a”
O
1
H
H
H
L
H
H
O
2
H
H
H
H
L
H
O
3
H
H
H
H
H
L
ENABLE “b”
E
b
H
X
L
L
L
L
E
b
X
H
L
L
L
L
O
0
H
H
L
H
H
H
OUTPUT “b”
O
1
H
H
H
L
H
H
O
2
H
H
H
H
L
H
O
3
H
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
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112
SN74LS156
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
I
OH
V
O
OL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Current
0.25
Output LOW Voltage
0.35
I
IH
I
IL
I
CC
Input HIGH Current
0.1
Input LOW Current
Power Supply Current
– 0.4
10
0.5
20
V
µA
mA
mA
mA
I
OL
= 8.0 mA
– 0.65
Min
2.0
0.8
– 1.5
100
0.4
Typ
Max
Unit
V
V
V
µA
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, V
OH
= MAX
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation Delay
Address, E
a
or E
b
to Output
Propagation Delay
Address to Output
Propagation Delay
E
a
to Output
Min
Typ
25
34
31
34
32
32
Max
40
51
46
51
48
48
Unit
ns
ns
ns
Figure 1
Figure 2
Figure 1
V
CC
= 5.0 V
C
L
= 15 pF
R
L
= 2.0 kΩ
Test Conditions
AC WAVEFORMS
V
IN
1.3 V
t
PHL
1.3 V
t
PLH
1.3 V
V
IN
1.3 V
t
PHL
1.3 V
t
PLH
1.3 V
V
OUT
1.3 V
V
OUT
1.3 V
Figure 1.
Figure 2.
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113
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