Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
General Description
The ICS8543 is a low skew, high performance 1-to-4
Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS) the ICS8543 provides a low power, low
noise, solution for distributing clock signals over controlled
impedances of 100Ω. The ICS8543 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The clock enable is internally synchronized to eliminate
runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8543 ideal for those applications demanding well defined
performance and repeatability.
ICS8543
DATA SHEET
Features
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Four differential LVDS output pairs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
Maximum output frequency: 800MHz
Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
Additive phase jitter, RMS: 0.164ps (typical)
Output skew: 40ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 2.6ns (maximum)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK_EN
Pullup
D
Q
CLK
Pulldown
nCLK
Pullup
PCLK
Pulldown
nPCLK
Pullup
CLK_SEL
Pulldown
LE
Pin Assignment
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
OE
GND
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DD
Q1
nQ1
Q2
nQ2
GND
Q3
nQ3
0
0
1
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
ICS8543
20-Lead TSSOP
6.5mm x 4.4mm x 0.925
mm
OE
Pullup
package body
G Package
Top View
ICS8543BG REVISION E DECEMBER 17, 2010
1
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
Name
GND
CLK_EN
Power
Input
Pullup
Type
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input. When
LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Output enable. Controls enabling and disabling of outputs Q[0:3], nQ[0:3].
LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
3
4
5
6
7
8
10, 18
11, 12
14, 15
16, 17
19, 20
CLK_SEL
CLK
nCLK
PCLK
nPCLK
OE
V
DD
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS8543BG REVISION E DECEMBER 17, 2010
2
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
OE
0
1
1
1
1
CLK_EN
X
0
0
1
1
CLK_SEL
X
0
1
0
1
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Selected Source
Q[0:3]
Hi-Z
Disabled; Low
Disabled; Low
Enabled
Enabled
Outputs
nQ[0:3]
Hi-Z
Disabled; High
Disabled; High
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Disabled
nCLK, nPCLK
CLK, PCLK
Enabled
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q[0:3]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ[0:3]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section,
Wiring the Differential Input to Accept Single-Ended Levels.
ICS8543BG REVISION E DECEMBER 17, 2010
3
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
73.2°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
OE, CLK_EN
Input High Current
CLK_SEL
OE, CLK_EN
I
IL
Input Low Current
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
Typical
Maximum
3.765
0.8
5
150
Units
V
V
µA
µA
µA
µA
ICS8543BG REVISION E DECEMBER 17, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
CLK
Input High Current
nCLK
CLK
I
IL
V
PP
V
CMR
Input Low Current
nCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVPECL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
PCLK
Input High Current
nPCLK
PCLK
I
IL
V
PP
V
CMR
Input Low Current
nPCLK
Peak-to-Peak Voltage
Common Mode Input Voltage;
NOTE 1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.3
1.5
1.0
V
DD
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
Table 4E. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
I
Oz
I
OFF
I
OSD
I
OS
V
OH
V
OL
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage
Power Off Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
Output Voltage Low
0.9
-10
-20
±1
-3.5
-3.5
1.34
1.06
1.125
Test Conditions
Minimum
200
Typical
280
0
1.25
5
Maximum
360
40
1.375
25
+10
+20
-5
-5
1.6
Units
mV
mV
V
mV
µA
µA
mA
mA
V
V
ICS8543BG REVISION E DECEMBER 17, 2010
5
©2010 Integrated Device Technology, Inc.
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