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IDT7133SA25PFB

Description
Dual-Port SRAM, 2KX16, 25ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size187KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT7133SA25PFB Overview

Dual-Port SRAM, 2KX16, 25ns, CMOS, PQFP100, TQFP-100

IDT7133SA25PFB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionTQFP-100
Contacts100
Reach Compliance Codenot_compliant
ECCN code3A001.A.2.C
Maximum access time25 ns
I/O typeCOMMON
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density32768 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize2KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP100,.63SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply5 V
Certification statusNot Qualified
Filter levelMIL-PRF-38535
Maximum seat height1.6 mm
Maximum standby current0.004 A
Minimum standby current2 V
Maximum slew rate0.33 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
Base Number Matches1
HIGH-SPEED
2K x 16 CMOS DUAL-PORT
STATIC RAMS
Integrated Device Technology, Inc.
IDT7133SA/LA
IDT7143SA/LA
FEATURES:
• High-speed access
— Military: 25/35/45/55/70/90ns (max.)
— Commercial: 20/25/35/45/55/70/90ns (max.)
• Low-power operation
— IDT7133/43SA
Active: 500 mW (typ.)
Standby: 5mW (typ.)
— IDT7133/43LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Versatile control for write: separate write control for
lower and upper byte of each port
• MASTER IDT7133 easily expands data bus width to 32
bits or more using SLAVE IDT7143
• On-chip port arbitration logic (IDT7133 only)
BUSY
output flag on IDT7133;
BUSY
input on IDT7143
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in 68-pin ceramic PGA, 68-pin Flatpack, 68-pin
PLCC, and 100-pin TQFP
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static
RAMs. The IDT7133 is designed to be used as a stand-alone
16-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or-
more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 32-bit-or-wider memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 500mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each port typically consuming 200µW for a 2V
battery.
The IDT7133/7143 devices have identical pinouts. Each is
packaged in a 68-pin ceramic PGA, a 68-pin flatpack, a 68-pin
PLCC, and a 100-pin TQFP. Military grade product is manu-
factured in compliance with the latest revision of MIL-STD-
883, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
FUNCTIONAL BLOCK DIAGRAM
R/
W
LUB(2)
CE
L
R/
CE
R
W
RUB(2)
R/
W
LLB(2)
OE
L
R/
W
RLB(2)
OE
R
I/O
8L
- I/O
15L
I/O
0L
- I/O
7L
I/O
CONTROL
I/O
CONTROL
I/O
8R
- I/O
15R
I/O
0R
- I/O
7R
BUSY
L(1)
A
10L
A
0L
ADDRESS
DECODER
11
BUSY
R(1)
MEMORY
ARRAY
ADDRESS
DECODER
11
A
10R
A
0R
NOTES:
1. IDT7133 (MASTER): BUSY is
open drain output and requires
pull-up resistor of 270Ω.
IDT7143 (SLAVE): BUSY is
input.
2. "LB" designates "Lower Byte"
and "UB" designates "Upper
Byte" for the R/
W
signals.
CE
L
ARBITRATION
LOGIC
(IDT7133 ONLY)
CE
R
2746 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2746/6
6.14
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