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IDT70T25L25PFG8

Description
Dual-Port SRAM, 8KX16, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100
Categorystorage    storage   
File Size160KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

IDT70T25L25PFG8 Overview

Dual-Port SRAM, 8KX16, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT70T25L25PFG8 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionPLASTIC, TQFP-100
Contacts100
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time25 ns
JESD-30 codeS-PQFP-G100
JESD-609 codee3
length14 mm
memory density131072 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX16
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)2.6 V
Minimum supply voltage (Vsup)2.4 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
Base Number Matches1
HIGH-SPEED 2.5V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
Features
PRELIMINARY
IDT70T35/34L
IDT70T25/24L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70T35/34L (IDT70T25/24L)
– Commercial: 20/25ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70T35/34L (IDT70T25/24L)
Active: 200mW (typ.)
Standby: 600
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70T35/34L (IDT70T25/24L) easily expands data bus
width to 36 bits (32 bits) or more using the Master/Slave
select when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 2.5V (±100mV) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP) package
and 100-pin fine pitch Ball Grid Array (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
0L
-I/O
8L
(4)
BUSY
L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
A
12R
(1)
A
0R
A
12L
(1)
A
0L
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
SEM
L
INT
L
(3)
NOTES:
1. A
12
is a NC for IDT70T34 and IDT70T24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70T25/24.
5. I/O
8
x - I/O
15
x for IDT70T25/24.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5639 drw 01
M/S
DECEMBER 2002
1
DSC-5639/2
©2002 Integrated Device Technology, Inc.
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