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Intel
®
945G/945GZ/945GC/
945P/945PL Express Chipset
Family
Datasheet
- For the Intel
®
82945G/82945GZ/82945GC Graphics and Memory
®
Controller Hub (GMCH) and Intel 82945P/82945PL Memory
Controller Hub (MCH)
June 2008
Document Number:
307502-005
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR
OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH may contain design defects or errors known as errata, which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Hyper-Threading Technology requires a computer system with an Intel Pentium 4 processor supporting HT Technology and a Hyper-Threading
Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See
http://www.intel.com/info/hyperthreading/ for more information including details on which processors support HT Technology.
Intel and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright 2005-2008, Intel Corporation
©
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Intel 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Contents
1
Introduction...................................................................................................................17
1.1
1.2
1.3
Terminology......................................................................................................21
Reference Documents ......................................................................................23
(G)MCH Overview ............................................................................................23
1.3.1
Host Interface ....................................................................................24
1.3.2
System Memory Interface ..................................................................24
1.3.3
Direct Media Interface (DMI) ..............................................................25
1.3.4
PCI Express* Interface (Intel
®
82945G/82945GC/82945P/82945PL
(G)MCH Only)....................................................................................26
Graphics (Intel
®
82945G/82945GC/82945GZ GMCH Only)...............................27
Analog and SDVO Displays (Intel
®
82945G/82945GC/82945GZ GMCH Only) ..29
1.5.1
System Interrupts...............................................................................29
1.5.2
(G)MCH Clocking...............................................................................29
1.5.3
Power Management ...........................................................................30
Host Interface Signals.......................................................................................33
DDR2 DRAM Channel A Interface ....................................................................36
DDR2 DRAM Channel B Interface ....................................................................37
DDR2 DRAM Reference and Compensation .....................................................38
PCI Express* Interface Signals (Intel
®
82945G/82945GC/82945P/82945PL
Only).................................................................................................................38
Analog Display Signals (Intel
®
82945G/82945GC/ 82945GZ GMCH Only) .......39
Clocks, Reset, and Miscellaneous.....................................................................40
Direct Media Interface (DMI).............................................................................41
Intel
®
Serial DVO (SDVO) Interface (Intel
®
82945G/82945GC/82945GZ GMCH
Only).................................................................................................................41
Power and Ground............................................................................................43
Reset States and Pull-up/Pull-downs.................................................................44
1.4
1.5
2
Signal Description .........................................................................................................31
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
Register Description......................................................................................................49
3.1
3.2
3.3
Register Terminology........................................................................................50
Platform Configuration......................................................................................50
Configuration Mechanisms................................................................................53
3.3.1
Standard PCI Configuration Mechanism ............................................53
3.3.2
PCI Express* Enhanced Configuration Mechanism (Intel
®
82945G/82945GC/82945P/82945PL (G)MCH Only)...........................53
Routing Configuration Accesses .......................................................................55
3.4.1
Internal Device Configuration Accesses .............................................56
3.4.2
Bridge Related Configuration Accesses .............................................57
3.4.2.1
PCI Express* Configuration Accesses (Intel
®
82945G/82945GC/82945P/82945PL (G)MCH Only) ..........57
3.4
Intel
®
82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
3
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3.5
3.4.2.2
DMI Configuration Accesses .............................................58
I/O Mapped Registers .......................................................................................58
3.5.1
CONFIG_ADDRESS—Configuration Address Register......................59
3.5.2
CONFIG_DATA—Configuration Data Register...................................60
Device 0 Configuration Register Details............................................................64
4.1.1
VID—Vendor Identification (D0:F0)....................................................64
4.1.2
DID—Device Identification (D0:F0) ....................................................64
4.1.3
PCICMD—PCI Command (D0:F0) .....................................................65
4.1.4
PCISTS—PCI Status (D0:F0) ............................................................66
4.1.5
RID—Revision Identification (D0:F0) .................................................67
4.1.6
CC—Class Code (D0:F0)...................................................................67
4.1.7
MLT—Master Latency Timer (D0:F0).................................................68
4.1.8
HDR—Header Type (D0:F0) ..............................................................68
4.1.9
SVID—Subsystem Vendor Identification (D0:F0) ...............................68
4.1.10 SID—Subsystem Identification (D0:F0)..............................................69
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) .............................................69
4.1.12 EPBAR—Egress Port Base Address (D0:F0) .....................................70
4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address
(D0:F0) ..............................................................................................71
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0)
®
(Intel 82945G/82945GC/82945P/82945PL (G)MCH Only) ................72
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ......74
4.1.16 GGC—GMCH Graphics Control Register (D0:F0) (Intel
®
82945G/82945GC/82945GZ GMCH Only) ........................................75
4.1.17 DEVEN—Device Enable (D0:F0) .......................................................76
4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0) ................................77
4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0) ................................78
4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0) ................................79
4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0) ................................80
4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0) ................................81
4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0) ................................82
4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0) ................................83
4.1.25 LAC—Legacy Access Control (D0:F0) ...............................................84
4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0)......................................85
4.1.27 SMRAM—System Management RAM Control (D0:F0).......................86
4.1.28 ESMRAMC—Extended System Management RAM Control (D0:F0) ..87
4.1.29 ERRSTS—Error Status (D0:F0) .........................................................88
4.1.30 ERRCMD—Error Command (D0:F0)..................................................89
4.1.31 SKPD—Scratchpad Data (D0:F0) ......................................................90
4.1.32 CAPID0—Capability Identifier (D0:F0) ...............................................90
MCHBAR Register ............................................................................................91
4.2.1
C0DRB0—Channel A DRAM Rank Boundary Address 0 ....................92
4.2.2
C0DRB1—Channel A DRAM Rank Boundary Address 1 ....................94
4.2.3
C0DRB2—Channel A DRAM Rank Boundary Address 2 ....................94
4.2.4
C0DRB3—Channel A DRAM Rank Boundary Address 3 ....................94
4.2.5
C0DRA0—Channel A DRAM Rank 0,1 Attribute ................................95
4.2.6
C0DRA2—Channel A DRAM Rank 2,3 Attribute ................................95
4.2.7
C0DCLKDIS—Channel A DRAM Clock Disable .................................96
4.2.8
C0BNKARC—Channel A DRAM Bank Architecture............................97
4.2.9
C0DRT1—Channel A DRAM Timing Register ....................................98
4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 ................................99
4
Host Bridge/DRAM Controller Registers (D0:F0) ...........................................................62
4.1
4.2
4
®
Intel 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
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4.3
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 ..............................101
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0 ..................101
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1 ..................101
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2 ..................101
4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3 ..................102
4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ..............................102
4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ..............................102
4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ...............................102
4.2.19 C1BNKARC—Channel B Bank Architecture.....................................102
4.2.20 C1DRT1—Channel B DRAM Timing Register 1 ...............................103
4.2.21 C1DRC0—Channel B DRAM Controller Mode 0 ..............................103
4.2.22 C1DRC1—Channel B DRAM Controller Mode 1 ..............................103
4.2.23 PMCFG—Power Management Configuration ...................................103
4.2.24 PMSTS—Power Management Status...............................................104
EPBAR Registers—Egress Port Register Summary ........................................105
4.3.1
EPESD—EP Element Self Description.............................................106
4.3.2
EPLE1D—EP Link Entry 1 Description.............................................107
4.3.3
EPLE1A—EP Link Entry 1 Address..................................................108
4.3.4
EPLE2D—EP Link Entry 2 Description.............................................108
4.3.5
EPLE2A—EP Link Entry 2 Address..................................................109
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Host-PCI Express* Bridge Registers (D1:F0) (Intel 82945G/82945GC/82945P/82945PL
Only)...........................................................................................................................110
5.1
Configuration Register Details (D1:F0)............................................................113
5.1.1
VID1—Vendor Identification (D1:F0) ................................................113
5.1.2
DID1—Device Identification (D1:F0) ................................................113
5.1.3
PCICMD1—PCI Command (D1:F0) .................................................114
5.1.4
PCISTS1—PCI Status (D1:F0) ........................................................116
5.1.5
RID1—Revision Identification (D1:F0) .............................................117
5.1.6
CC1—Class Code (D1:F0) ...............................................................117
5.1.7
CL1—Cache Line Size (D1:F0) ........................................................118
5.1.8
HDR1—Header Type (D1:F0) ..........................................................118
5.1.9
PBUSN1—Primary Bus Number (D1:F0) .........................................118
5.1.10 SBUSN1—Secondary Bus Number (D1:F0).....................................119
5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ................................119
5.1.12 IOBASE1—I/O Base Address (D1:F0)..............................................120
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ..............................................120
5.1.14 SSTS1—Secondary Status (D1:F0) .................................................121
5.1.15 MBASE1—Memory Base Address (D1:F0) ......................................122
5.1.16 MLIMIT1—Memory Limit Address (D1:F0) .......................................123
5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ...............124
5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) ................125
5.1.19 CAPPTR1—Capabilities Pointer (D1:F0) .........................................125
5.1.20 INTRLINE1—Interrupt Line (D1:F0) .................................................126
5.1.21 INTRPIN1—Interrupt Pin (D1:F0).....................................................126
5.1.22 BCTRL1—Bridge Control (D1:F0) ....................................................127
5.1.23 PM_CAPID1—Power Management Capabilities (D1:F0)..................129
5.1.24 PM_CS1—Power Management Control/Status (D1:F0)....................130
5.1.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ......131
5.1.26 SS—Subsystem ID and Subsystem Vendor ID (D1:F0)....................131
5.1.27 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0)....132
5.1.28 MC—Message Control (D1:F0) ........................................................133
5.1.29 MA—Message Address (D1:F0) .......................................................134
Intel
®
82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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