813078BYILFT datasheet, PDF - EEWORLD Datasheet

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813078BYILFT: DescriptionTQFP-64, Reel; CategoryThe embedded processor and controller Microcontrollers and processors; File Size741KB，27 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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813078BYILFT Overview

TQFP-64, Reel

813078BYILFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	TQFP-64
Contacts	64
Manufacturer packaging code	EDG64P2
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
Humidity sensitivity level	3
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	614.4 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	HTFQFP
Package shape	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	30.72 MHz
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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Femtoclocks™ VCXO-PLL Frequency Generator

for Wireless Infrastructure Equipment

Data Sheet

813078I

OBSOLETE

General Description

The ICS813078I is a member of the HiperClocks family of high

performance clock solutions from IDT. The ICS813078I a PLL

based synchronous clock solution that is optimized for wireless

infrastructure equipment where frequency translation and jitter

attenuation is needed.

The device contains two internal PLL stages that are cascaded in

series. The first PLL stage attenuates the reference clock jitter by

using an internal or external VCXO circuit. The internal VCXO

requires the connection of an external inexpensive pullable crystal

(XTAL) to the ICS813078I. This first PLL stage (VCXO PLL) uses

external passive loop filter components which are used to

optimize the PLL loop bandwidth and damping characteristics for

the given application. The output of the first stage VCXO PLL is a

stable and jitter-tolerant 30.72MHz reference input for the second

PLL stage. The second PLL stage provides frequency translation

by multiplying the output of the first stage up to 491.52MHz or

614.4MHz. The low phase noise characteristics of the VCXO-PLL

clock signal is maintained by the internal FemtoClock™ PLL,

which requires no external components or complex programming.

Two independently configurable frequency dividers translate the

internal VCO signal to the desired output frequencies. All

frequency translation ratios are set by device configuration pins.

Supported input reference clock frequencies:

10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz,

61.44MHz, and 122.88MHz

Supported output clock frequencies:

30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz,

153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz

Features

•

Nine outputs, organized in three independent output banks with

differential LVPECL and single-ended outputs

One differential input clock can accept the following differential

input levels: LVDS, LVPECL, LVHSTL

One single-ended clock input

Frequency generation optimized for wireless infrastructure

Attenuates the phase jitter of the input clock signal by using

low-cost pullable fundamental mode crystal (XTAL)

Internal Femtoclock frequency multiplier stage eliminates the

need for an expensive external high frequency VCXO

LVCMOS levels for all control I/O

RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal

(12kHz to 20MHz): 1.1ps rms (typical)

RMS phase jitter @ 61.44MHz, using a 30.72MHz crystal

(12kHz to 20MHz): 0.97ps rms (typical)

VCXO PLL bandwidth can be optimized for jitter attenuation and

reference frequency tracking using external loop filter

components

PLL fast-lock control

PLL lock detect output

Absolute pull range is +/-50 ppm

Full 3.3V supply voltage

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

For replacement device use 8T49N285-dddNLGI

Pin Assignment

XTAL__IN

XTAL_OUT

QC1

QC2

CCO_CMOS

QC3

LOCK

QC0

CCO_CMOS

LF1

LF0

ISET

FLM

CLK1

REF_SEL

nMR

CLK0

nCLK0

NA1

NA0

NB1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

64-Lead TQFP, E-Pad

10mm x 10mm x 1mm

package body

Y Package

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

NB0

NC1

NC0

BYPASS1

BYPASS0

CCA

nSTOPA

nSTOPB

nSTOPC

QB1

nQB1

CCO

nQA0

QA0

nQA1

QA1

CCO

nQA2

QA2

nQB0

QB0

CCO

July 29, 2016

813078BYILFT Related Products

	813078BYILFT	813078BYILF
Description	TQFP-64, Reel	TQFP-64, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP
package instruction	TQFP-64	TQFP-64
Contacts	64	64
Manufacturer packaging code	EDG64P2	EDG64P2
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
JESD-30 code	S-PQFP-G64	S-PQFP-G64
JESD-609 code	e3	e3
length	10 mm	10 mm
Humidity sensitivity level	3	3
Number of terminals	64	64
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	614.4 MHz	614.4 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HTFQFP	HTFQFP
Package shape	SQUARE	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260
Master clock/crystal nominal frequency	30.72 MHz	30.72 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	10 mm	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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