Femtoclocks™ VCXO-PLL Frequency Generator
for Wireless Infrastructure Equipment
Data Sheet
813078I
OBSOLETE
General Description
The ICS813078I is a member of the HiperClocks family of high
performance clock solutions from IDT. The ICS813078I a PLL
based synchronous clock solution that is optimized for wireless
infrastructure equipment where frequency translation and jitter
attenuation is needed.
The device contains two internal PLL stages that are cascaded in
series. The first PLL stage attenuates the reference clock jitter by
using an internal or external VCXO circuit. The internal VCXO
requires the connection of an external inexpensive pullable crystal
(XTAL) to the ICS813078I. This first PLL stage (VCXO PLL) uses
external passive loop filter components which are used to
optimize the PLL loop bandwidth and damping characteristics for
the given application. The output of the first stage VCXO PLL is a
stable and jitter-tolerant 30.72MHz reference input for the second
PLL stage. The second PLL stage provides frequency translation
by multiplying the output of the first stage up to 491.52MHz or
614.4MHz. The low phase noise characteristics of the VCXO-PLL
clock signal is maintained by the internal FemtoClock™ PLL,
which requires no external components or complex programming.
Two independently configurable frequency dividers translate the
internal VCO signal to the desired output frequencies. All
frequency translation ratios are set by device configuration pins.
Supported input reference clock frequencies:
10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz,
61.44MHz, and 122.88MHz
Supported output clock frequencies:
30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz,
153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Nine outputs, organized in three independent output banks with
differential LVPECL and single-ended outputs
One differential input clock can accept the following differential
input levels: LVDS, LVPECL, LVHSTL
One single-ended clock input
Frequency generation optimized for wireless infrastructure
Attenuates the phase jitter of the input clock signal by using
low-cost pullable fundamental mode crystal (XTAL)
Internal Femtoclock frequency multiplier stage eliminates the
need for an expensive external high frequency VCXO
LVCMOS levels for all control I/O
RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal
(12kHz to 20MHz): 1.1ps rms (typical)
RMS phase jitter @ 61.44MHz, using a 30.72MHz crystal
(12kHz to 20MHz): 0.97ps rms (typical)
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference frequency tracking using external loop filter
components
PLL fast-lock control
PLL lock detect output
Absolute pull range is +/-50 ppm
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For replacement device use 8T49N285-dddNLGI
Pin Assignment
V
EE
XTAL__IN
XTAL_OUT
QC1
V
EE
QC2
V
CCO_CMOS
QC3
V
EE
V
CC
MF
LOCK
V
EE
QC0
V
CCO_CMOS
nc
LF1
LF0
ISET
nc
FLM
V
CC
V
CC
CLK1
REF_SEL
nMR
CLK0
nCLK0
V
EE
NA1
NA0
NB1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
3
46
4
45
5
44
43
6
64-Lead TQFP, E-Pad
7
42
10mm x 10mm x 1mm
8
41
package body
9
40
Y Package
10
39
11
38
12
37
13
36
14
35
1
2
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NB0
NC1
NC0
R2
R1
R0
BYPASS1
BYPASS0
nc
nc
V
CCA
nSTOPA
nSTOPB
nSTOPC
QB1
nQB1
nc
nc
V
CCO
nQA0
QA0
V
EE
nQA1
QA1
V
CCO
nQA2
QA2
V
CC
V
EE
nQB0
QB0
V
CCO
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
Block Diagram
XTAL_IN
LF0
ISET
LF1
XTAL_OUT
f
XTAL
= 30.72MHz
LOCK
nSTOPA
f
OUT
QA0
nQA0
QA1
nQA1
QA2
nQA2
f
REF
CLK0
nCLK0
CLK1
f
VCXO
f
PD
f
VCO
11
10
Femto
PLL
÷16,
÷20
NA
÷2, ÷4
÷5, ÷8
0
0
1
P
÷1, ÷2,
÷4, ÷5,
÷125
PD
CP
VCXO
0x
NB
÷1, ÷4
÷5, ÷8
QB0
nQB0
QB1
nQB1
REF_SEL
3
MV
÷1, ÷2, ÷12,
÷192, ÷256, ÷384
LUT
Multiplier
R[2:0]
FLM
MF
BYPASS[1:0]
nSTOPB
Internal VCXO
2
QC0
NC
÷4, ÷5,
÷8, ÷16
NA[1:0]
NB[1:0]
NC[1:0]
nMR
nSTOPC
QC1
QC2
QC3
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
Table 1. Pin Descriptions
Number
1
2
3
4, 25, 26,
47, 48, 49
5
6, 7, 37, 61
8
9
10
11
12
13, 36, 43,
50, 54, 58, 64
14. 15
16, 17
18, 19
20, 21, 22
23,
24
27
28
29
30
31, 32
33, 40, 46
34, 35
38, 39
41, 42
44, 45
Name
LF1
LF0
ISET
nc
FLM
V
CC
CLK1
REF_SEL
nMR
CLK0
nCLK0
V
EE
NA1, NA0
NB1, NB0
NC1, NC0
R2, R1, R0
BYPASS1,
BYPASS0
V
CCA
nSTOPA
nSTOPB
nSTOPC
QB1, nQB1
V
CCO
QB0, nQB0
QA2, nQA2
QA1, nQA1
QA0, nQA0
QC3, QC2,
QC1, QC0
V
CCO_CMOS
Analog
Input
Analog
Output
Analog
Unused
Input
Power
Input
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Power
Input
Input
Input
Output
Power
Output
Output
Output
Output
Pullup
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Input from external loop filter. VCXO control voltage input.
Output to external loop filter. Charge pump output.
Charge pump current-settings pin.
No connect.
VCXO-PLL fast lock mode. See Table 3H. LVCMOS/LVTTL interface levels.
Power supply pins for LVPECL outputs.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects the input reference clock. See Table 3F.
LVCMOS/LVTTL interface levels.
Master reset. See Table 3I. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Negative supply pins.
Femto-PLL output-divider for QAn/nQAn outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Femto-PLL output-divider for QBn/nQBn outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Femto-PLL output-divider for QCn outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
VCXO-PLL pre-divider and VCXO multiplier selection. See Table 3A.
LVCMOS/LVTTL interface levels.
PLL mode selections. See Table 3G. LVCMOS/LVTTL interface levels.
Analog supply pin.
Output clock stop for Bank A. See Table 3J. LVCMOS/LVTTL interface levels.
Output clock stop for Bank B. See Table 3K. LVCMOS/LVTTL interface levels.
Output clock stop for Bank C. See Table 3L. LVCMOS/LVTTL interface levels.
Bank B output pair. LVPECL interface levels.
Output supply pins for LVPECL outputs.
Bank B output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
continued on next page.
51, 53, 55, 57
52, 56
Output
Power
Single-ended Bank C outputs. LVCMOS/LVTTL interface levels.
Output supply pins for LVCMOS outputs.
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
Number
59
60
62, 63
Name
LOCK
MF
XTAL_OUT,
XTAL_IN
Output
Input
Input
Type
Description
VCXO lock state. LVCMOS/LVTTL interface levels. See Table 3M.
FemtoClock-PLL feedback divider selection. See Table 3E.
LVCMOS/LVTTL interface levels.
Internal VCXO crystal oscillator interface.
XTAL_IN is the input. XTAL_OUT is the output.
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
Parameter
Input Capacitance
Power Dissipation
Capacitance (per output)
Input Pullup Resistor
V
CC
= V
CCO_CMOS
= 3.465V
Test Conditions
Minimum
Typical
4
10
51
51
15
Maximum
Units
pF
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
R
OUT
Output Impedance
QC[3:0]
D
EVICE
C
ONFIGURATION
The ICS813078I is a two stage device, a VCXO-PLL stage
followed by a low phase noise FemtoClock PLL multiplier stage.
The VCXO-PLL stage uses a pullable crystal to lock to the
reference clock. The low phase noise FemtoClock multiplies the
VCXO-PLL output clock up to 491.52MHz or 614.4MHz and three
independent output dividers scale the frequency down to the
desired output frequencies. With a given input and VCXO
frequency, the output frequency is a function of the P, MF, MV and
the NA, NB and NC dividers. The P and MV are controlled by the
R[2:0] control pins through the internal lookup table (LUT).
The VCXO-PLL pre-divider (P) down-scales the input reference
frequency f
REF
and enables the use of the ICS813078I at a variety
of input frequencies. P and MV must be set to match the VCXO
frequency: f
REF
÷ P = f
VCXO
÷ MV. For example, at the nominal
VCXO frequency of 30.72MHz and if MV equals one, the input
frequency must be an integer multiple of 30.72MHz (for MV = 2,
the input frequency must be an integer multiple of 15.36MHz). The
FemtoClock PLL stage multiplies the VCXO frequency
(30.72MHz) to 614.4MHz or 491.52MHz by a multiplier MF of 20
or 16. The output frequency equals [(f
REF
÷ P) * MV * MF] ÷ NA,
NB, or NC. The NA, NB and NC dividers operate independently.
Table 3A. Input Frequency Configuration Example
Table (fVCXO = 30.72MHz)
fref
(MHz)
30.72
61.44
122.88
15.36
10
12.8
15
20
Input
R[2:0]
000
001
010
011
100
101
110
111
Internal Dividers
P
1
2
4
1
125
5
125
125
MV
1
1
1
2
384
12
256
192
fXTAL
(MHz)
30.72
30.72
30.72
30.72
30.72
30.72
30.72
30.72
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
Table 3B. PLL Output-Divider (NA) Configuration Table.
Inputs
NA1
0 (default)
0
1
1
NA0
0 (default)
1
0
1
QAn Output
Frequency (MHz)
Operation
f
QAn
= f
VCO
÷ 2
f
QAn
= f
VCO
÷ 4
f
QAn
= f
VCO
÷ 5
f
QAn
= f
VCO
÷ 8
MF = 0
245.76
122.88
98.304
61.44
MF = 1
307.2
153.6
122.88
76.8
Output-Divider
NA
2
4
5
8
Table 3C. PLL Output-Divider (NB) Configuration Table.
Inputs
NB1
0 (default)
0
1
1
NB0
0 (default)
1
0
1
QBn Output
Frequency (MHz)
Operation
f
QBn
= f
VCO
÷ 1
f
QBn
= f
VCO
÷ 4
f
QBn
= f
VCO
÷ 5
f
QBn
= f
VCO
÷ 8
MF = 0
491.52
122.88
98.304
61.44
MF = 1
614.4
153.6
122.88
76.8
Output-Divider
NB
1
4
5
8
Table 3D. PLL Output-Divider (NC) Configuration Table.
Inputs
NC1
0 (default)
0
1
1
NC0
0 (default)
1
0
1
QCn Output
Frequency (MHz)
Operation
f
QCn
= f
VCO
÷ 4
f
QCn
= f
VCO
÷ 5
f
QCn
= f
VCO
÷ 8
f
QCn
= f
VCO
÷ 16
MF = 0
122.08
98.304
61.44
30.72
MF = 1
153.6
122.88
76.8
38.4
Output-Divider
NC
4
5
8
16
Table 3E. Femtoclock PLL Feedback Divider (MF) Configuration Table (f
XTAL
= 30.72MHz)
Input
MF
0 (default)
1
Feedback Divider MF
16
20
Operation
f
VCO
= f
VCXO
x 16 = 491.52MHz
f
VCO
= f
VCXO
x 20 = 614.4MHz
© 2016 Integrated Device Technology, Inc
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July 29, 2016
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