RB80526PY700256 datasheet, PDF

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RB80526PY700256: Description32-BIT, 700MHz, MICROPROCESSOR, CPGA370, FCPGA-370; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，81 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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RB80526PY700256 Overview

32-BIT, 700MHz, MICROPROCESSOR, CPGA370, FCPGA-370

RB80526PY700256 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Maker	Rochester Electronics
Parts packaging code	PGA
package instruction	FCPGA-370
Contacts	370
Reach Compliance Code	unknown
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P370
JESD-609 code	e3
length	49.53 mm
low power mode	YES
Humidity sensitivity level	1
Number of terminals	370
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA
Package shape	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH
Peak Reflow Temperature (Celsius)	225
Certification status	COMMERCIAL
Maximum seat height	2.978 mm
speed	700 MHz
Nominal supply voltage	1.65 V
surface mount	NO
Terminal surface	MATTE TIN
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Pentium

III Processor for the PGA370 Socket at 500 MHz to 1 GHz

Contents

1.0

Introduction......................................................................................................................... 7

1.1

Terminology........................................................................................................... 8

1.1.1 Package and Processor Terminology ...................................................... 8

1.1.2 Processor Naming Convention.................................................................9

Related Documents.............................................................................................10

Processor System Bus and V

REF

........................................................................11

Clock Control and Low Power States..................................................................12

2.2.1 Normal State—State 1 ...........................................................................13

2.2.2 AutoHALT Powerdown State—State 2...................................................13

2.2.3 Stop-Grant State—State 3 .....................................................................13

2.2.4 HALT/Grant Snoop State—State 4 ........................................................14

2.2.5 Sleep State—State 5..............................................................................14

2.2.6 Deep Sleep State—State 6 ....................................................................14

2.2.7 Clock Control..........................................................................................15

Power and Ground Pins ......................................................................................15

2.3.1 Phase Lock Loop (PLL) Power...............................................................16

Decoupling Guidelines .......................................................................................16

2.4.1 Processor VCC

CORE

Decoupling............................................................16

2.4.2 Processor System Bus AGTL+ Decoupling............................................16

Processor System Bus Clock and Processor Clocking .......................................17

2.5.1 Mixing Processors of Differrent Frequencies .........................................17

Voltage Identification ...........................................................................................17

Processor System Bus Unused Pins...................................................................19

Processor System Bus Signal Groups ................................................................19

2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................20

2.8.2 System Bus Frequency Select Signals (BSEL[1:0]) ...............................21

Test Access Port (TAP) Connection....................................................................22

Maximum Ratings................................................................................................22

Processor DC Specifications...............................................................................23

AGTL+ System Bus Specifications .....................................................................29

System Bus AC Specifications ............................................................................29

2.13.1 I/O Buffer Model .....................................................................................30

BCLK and PICCLK Signal Quality Specifications and Measurement Guidelines 38

AGTL+ Signal Quality Specifications and Measurement Guidelines ..................39

AGTL+ Signal Quality Specifications and Measurement Guidelines ..................40

3.3.1 Overshoot/Undershoot Guidelines .........................................................40

3.3.2 Overshoot/Undershoot Magnitude .........................................................41

3.3.3 Overshoot/Undershoot Pulse Duration...................................................41

3.3.4 Activity Factor .........................................................................................41

3.3.5 Reading Overshoot/Undershoot Specification Tables............................42

3.3.6 Determining if a System meets the Overshoot/Undershoot

Specifications .........................................................................................43

1.2

2.0

2.1

2.2

Electrical Specifications....................................................................................................11

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

3.0

Signal Quality Specifications ............................................................................................38

3.1

3.2

3.3

Datasheet

Pentium

III Processor for the PGA370 Socket at 500 MHz to 1 GHz

3.4

Non-AGTL+ Signal Quality Specifications and Measurement Guidelines........... 45

3.4.1 Overshoot/Undershoot Guidelines ......................................................... 46

3.4.2 Ringback Specification........................................................................... 46

3.4.3 Settling Limit Guideline .......................................................................... 46

Thermal Specifications........................................................................................ 47

4.1.1 Thermal Diode........................................................................................ 48

FC-PGA Mechanical Specifications .................................................................... 50

Processor Markings ............................................................................................ 52

Processor Signal Listing...................................................................................... 52

Mechanical Specifications for the Boxed Intel

Pentium

III Processor.............. 64

6.1.1 Boxed Processor Thermal Cooling Solution Dimensions....................... 64

6.1.2 Boxed Processor Heatsink Weight......................................................... 67

6.1.3 Boxed Processor Thermal Cooling Solution Clip ................................... 67

Thermal Specifications........................................................................................ 68

6.2.1 Boxed Processor Cooling Requirements ............................................... 68

Electrical Requirements for the Boxed Intel

Pentium

III Processor................. 69

6.3.1 Fan Heatsink Power Supply ................................................................... 69

Alphabetical Signals Reference .......................................................................... 71

Signal Summaries ............................................................................................... 78

4.0

Thermal Specifications and Design Considerations......................................................... 47

4.1

5.0

Mechanical Specifications............................................................................................... 50

5.1

5.2

5.3

6.0

Boxed Processor Specifications....................................................................................... 64

6.1

6.2

6.3

7.0

Processor Signal Description ........................................................................................... 71

7.1

7.2

Datasheet

RB80526PY700256 Related Products

	RB80526PY700256	RB80526PY850256	RB80526PY600256
Description	32-BIT, 700MHz, MICROPROCESSOR, CPGA370, FCPGA-370	32-BIT, 850MHz, MICROPROCESSOR, CPGA370, FCPGA-370	32-BIT, 600 MHz, MICROPROCESSOR, CPGA370, FCPGA-370
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics
Parts packaging code	PGA	PGA	PGA
package instruction	FCPGA-370	FCPGA-370	IPGA,
Contacts	370	370	370
Reach Compliance Code	unknown	unknown	unknown
Address bus width	36	36	36
bit size	32	32	32
boundary scan	YES	YES	YES
maximum clock frequency	100 MHz	100 MHz	133 MHz
External data bus width	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES
JESD-30 code	S-CPGA-P370	S-CPGA-P370	S-CPGA-P370
length	49.53 mm	49.53 mm	49.53 mm
low power mode	YES	YES	YES
Number of terminals	370	370	370
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA	IPGA	IPGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL
Maximum seat height	2.978 mm	2.978 mm	2.978 mm
speed	700 MHz	850 MHz	600 MHz
Nominal supply voltage	1.65 V	1.65 V	1.65 V
surface mount	NO	NO	NO
Terminal surface	MATTE TIN	MATTE TIN	NOT SPECIFIED
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	49.53 mm	49.53 mm	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Base Number Matches	1	1	1
Is it lead-free?	Lead free	Lead free	-
JESD-609 code	e3	e3	-
Humidity sensitivity level	1	1	-
Peak Reflow Temperature (Celsius)	225	225	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-

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